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3 changes: 3 additions & 0 deletions llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
Original file line number Diff line number Diff line change
Expand Up @@ -8880,12 +8880,15 @@ void AArch64TargetLowering::AdjustInstrPostInstrSelection(MachineInstr &MI,
MI.removeOperand(I);

// The SVE vector length can change when entering/leaving streaming mode.
// FPMR is set to 0 when entering/leaving streaming mode.
if (MI.getOperand(0).getImm() == AArch64SVCR::SVCRSM ||
MI.getOperand(0).getImm() == AArch64SVCR::SVCRSMZA) {
MI.addOperand(MachineOperand::CreateReg(AArch64::VG, /*IsDef=*/false,
/*IsImplicit=*/true));
MI.addOperand(MachineOperand::CreateReg(AArch64::VG, /*IsDef=*/true,
/*IsImplicit=*/true));
MI.addOperand(MachineOperand::CreateReg(AArch64::FPMR, /*IsDef=*/true,
/*IsImplicit=*/true));
}
}

Expand Down
23 changes: 23 additions & 0 deletions llvm/test/CodeGen/AArch64/sme-write-fpmr.ll
Original file line number Diff line number Diff line change
@@ -0,0 +1,23 @@
; RUN: llc -mattr=+sme -stop-after=finalize-isel < %s | FileCheck %s

target triple = "aarch64"

; Check that we don't define FPMR for 'smstart za' and 'smstop za'
define void @smstart_za() "aarch64_new_za" nounwind {
; CHECK-LABEL: name: smstart_za
; CHECK-NOT: implicit-def {{[^,]*}}$fpmr
ret void
}

; Check that we do define FPMR for 'smstart sm' and 'smstop sm'
define void @smstart_sm() nounwind {
; CHECK-LABEL: name: smstart_sm
; CHECK: MSRpstatesvcrImm1 1, 1,
; CHECK-SAME: implicit-def {{[^,]*}}$fpmr
; CHECK: MSRpstatesvcrImm1 1, 0,
; CHECK-SAME: implicit-def {{[^,]*}}$fpmr
call void @require_sm()
ret void
}

declare void @require_sm() "aarch64_pstate_sm_enabled"
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