Skip to content

[BOLT][RISCV] Fix MCPlusBuilder instrumentation ifaces #136211

New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Merged
kazutakahirata merged 1 commit into from
Apr 17, 2025
Merged

[BOLT][RISCV] Fix MCPlusBuilder instrumentation ifaces #136211

Changes from all commits
Commits
Show all changes
1 commit
Select commit
File filter

Filter by extension

Filter by extension
Conversations
Failed to load comments.
Loading
Jump to
Jump to file
Failed to load files.
Loading
Diff view
Diff view
15 changes: 7 additions & 8 deletions bolt/lib/Target/RISCV/RISCVMCPlusBuilder.cpp
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -555,9 +555,9 @@ class RISCVMCPlusBuilder : public MCPlusBuilder {
.addReg(RegCnt);
}

InstructionListType createCmpJE(MCPhysReg RegNo, MCPhysReg RegTmp,
const MCSymbol *Target,
MCContext *Ctx) const {
InstructionListType createRegCmpJE(MCPhysReg RegNo, MCPhysReg RegTmp,
const MCSymbol *Target,
MCContext *Ctx) const {
InstructionListType Insts;
Insts.emplace_back(
MCInstBuilder(RISCV::SUB).addReg(RegTmp).addReg(RegNo).addReg(RegNo));
Expand Down Expand Up @@ -718,7 +718,7 @@ class RISCVMCPlusBuilder : public MCPlusBuilder {
Insts.emplace_back();
loadReg(Insts.back(), RISCV::X10, RISCV::X10, 0);
InstructionListType cmpJmp =
createCmpJE(RISCV::X10, RISCV::X11, IndCallHandler, Ctx);
createRegCmpJE(RISCV::X10, RISCV::X11, IndCallHandler, Ctx);
Insts.insert(Insts.end(), cmpJmp.begin(), cmpJmp.end());
Insts.emplace_back();
createStackPointerIncrement(Insts.back(), 16);
Expand Down Expand Up @@ -777,14 +777,13 @@ class RISCVMCPlusBuilder : public MCPlusBuilder {
return createGetter(Ctx, "__bolt_instr_num_funcs");
}

void convertIndirectCallToLoad(MCInst &Inst, MCPhysReg Reg,
MCPhysReg ZeroReg) const {
void convertIndirectCallToLoad(MCInst &Inst, MCPhysReg Reg) override {
bool IsTailCall = isTailCall(Inst);
if (IsTailCall)
removeAnnotation(Inst, MCPlus::MCAnnotation::kTailCall);
Inst.setOpcode(RISCV::ADD);
Inst.insert(Inst.begin(), MCOperand::createReg(Reg));
Inst.insert(Inst.begin() + 1, MCOperand::createReg(ZeroReg));
Inst.insert(Inst.begin() + 1, MCOperand::createReg(RISCV::X0));
return;
}

Expand Down Expand Up @@ -845,7 +844,7 @@ class RISCVMCPlusBuilder : public MCPlusBuilder {
InstructionListType Insts;
spillRegs(Insts, {RISCV::X10, RISCV::X11});
Insts.emplace_back(CallInst);
convertIndirectCallToLoad(Insts.back(), RISCV::X10, RISCV::X0);
convertIndirectCallToLoad(Insts.back(), RISCV::X10);
InstructionListType LoadImm = createLoadImmediate(RISCV::X11, CallSiteID);
Insts.insert(Insts.end(), LoadImm.begin(), LoadImm.end());
spillRegs(Insts, {RISCV::X10, RISCV::X11});
Expand Down
Loading