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[RISCV] Strengthen register usage validation for XTheadMemPair loads #136241

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Merged
el-ev merged 2 commits into from
Apr 18, 2025
Merged

[RISCV] Strengthen register usage validation for XTheadMemPair loads #136241

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93b41b7
[RISCV] Strengthen register usage validation for XTheadMemPair loads
el-ev Apr 18, 2025
67795f8
rv64xtheadmempair-invalid.s
el-ev Apr 18, 2025
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4 changes: 2 additions & 2 deletions llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
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Expand Up @@ -3648,9 +3648,9 @@ bool RISCVAsmParser::validateInstruction(MCInst &Inst,
MCRegister Rd2 = Inst.getOperand(1).getReg();
MCRegister Rs1 = Inst.getOperand(2).getReg();
// The encoding with rd1 == rd2 == rs1 is reserved for XTHead load pair.
if (Rs1 == Rd1 && Rs1 == Rd2) {
if (Rs1 == Rd1 || Rs1 == Rd2 || Rd1 == Rd2) {
SMLoc Loc = Operands[1]->getStartLoc();
return Error(Loc, "rs1, rd1, and rd2 cannot all be the same");
return Error(Loc, "rs1, rd1, and rd2 cannot overlap");
}
}

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3 changes: 2 additions & 1 deletion llvm/test/MC/RISCV/rv32xtheadmempair-invalid.s
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Expand Up @@ -15,6 +15,7 @@ th.lwd a3, a4, (a5), 3, 5 # CHECK: [[@LINE]]:25: error: operand must be consta
th.swd t3, t4, (t5), 5, 4 # CHECK: [[@LINE]]:22: error: immediate must be an integer in the range [0, 3]
th.swd t3, t4, (t5) # CHECK: [[@LINE]]:1: error: too few operands for instruction
th.swd t3, t4, (t5), 3, 5 # CHECK: [[@LINE]]:25: error: operand must be constant 3
th.lwud x6, x6, (x6), 2, 3 # CHECK: [[@LINE]]:9: error: rs1, rd1, and rd2 cannot all be the same
th.lwd x6, x7, (x7), 2, 3 # CHECK: [[@LINE]]:8: error: rs1, rd1, and rd2 cannot overlap
th.lwud x6, x6, (x6), 2, 3 # CHECK: [[@LINE]]:9: error: rs1, rd1, and rd2 cannot overlap
th.ldd t0, t1, (t2), 2, 4 # CHECK: [[@LINE]]:1: error: instruction requires the following: RV64I Base Instruction Set{{$}}
th.sdd t0, t1, (t2), 2, 4 # CHECK: [[@LINE]]:1: error: instruction requires the following: RV64I Base Instruction Set{{$}}
3 changes: 2 additions & 1 deletion llvm/test/MC/RISCV/rv64xtheadmempair-invalid.s
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Expand Up @@ -15,4 +15,5 @@ th.lwd a3, a4, (a5), 3, 5 # CHECK: [[@LINE]]:25: error: operand must be consta
th.swd t3, t4, (t5), 5, 4 # CHECK: [[@LINE]]:22: error: immediate must be an integer in the range [0, 3]
th.swd t3, t4, (t5) # CHECK: [[@LINE]]:1: error: too few operands for instruction
th.swd t3, t4, (t5), 3, 5 # CHECK: [[@LINE]]:25: error: operand must be constant 3
th.lwud x6, x6, (x6), 2, 3 # CHECK: [[@LINE]]:9: error: rs1, rd1, and rd2 cannot all be the same
th.ldd x6, x6, (x7), 2, 3 # CHECK: [[@LINE]]:8: error: rs1, rd1, and rd2 cannot overlap
th.lwud x6, x6, (x6), 2, 3 # CHECK: [[@LINE]]:9: error: rs1, rd1, and rd2 cannot overlap
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