Experimental patch for understanding the pre-RA MachineScheduler

llvm/include/llvm/CodeGen/MachineScheduler.h

@@ -411,6 +411,24 @@ class ScheduleDAGMI : public ScheduleDAGInstrs {
 /// ScheduleDAGMILive is an implementation of ScheduleDAGInstrs that schedules
 /// machine instructions while updating LiveIntervals and tracking regpressure.
 class ScheduleDAGMILive : public ScheduleDAGMI {
+
+  // Count register overlaps before and after scheduling in order to print
+  // the difference once per region along with its region ID. Enabled with
+  // -sched-print-pressures.
+  struct RegOverlaps {
+    int GPR;
+    int FP;
+    int GPRMax;
+    int FPMax;
+    RegOverlaps() : GPR(0), FP(0), GPRMax(0), FPMax(0) {}
+  };
+  void countRegOverlaps(RegOverlaps &RO, MachineBasicBlock::iterator FirstItr,
+                        MachineBasicBlock::iterator EndItr) const;
+
+  // Show liveness visually of registers before and after scheduling. Enabled
+  // with -sched-show-ints and -misched-only-block=NUM.
+  void showIntervals(std::string Msg, std::string I, MachineBasicBlock *MBB) const;
+
 protected:
   RegisterClassInfo *RegClassInfo;
 
@@ -1197,8 +1215,10 @@ class GenericSchedulerBase : public MachineSchedStrategy {
   const TargetSchedModel *SchedModel = nullptr;
   const TargetRegisterInfo *TRI = nullptr;
 
+public:
   MachineSchedPolicy RegionPolicy;
 
+protected:
   SchedRemainder Rem;
 
   GenericSchedulerBase(const MachineSchedContext *C) : Context(C) {}

llvm/include/llvm/CodeGen/ScheduleDAGInstrs.h

@@ -396,6 +396,9 @@ namespace llvm {
 
     /// Returns true if the def register in \p MO has no uses.
     bool deadDefHasNoUse(const MachineOperand &MO);
+
+  public:
+    unsigned CurrRegionIdx;
   };
 
   /// Creates a new SUnit and return a ptr to it.

llvm/include/llvm/CodeGen/SlotIndexes.h

@@ -96,9 +96,11 @@ class raw_ostream;
       return lie.getPointer();
     }
 
+  public:
     unsigned getIndex() const {
       return listEntry()->getIndex() | getSlot();
     }
+  private:
 
     /// Returns the slot for this SlotIndex.
     Slot getSlot() const {

llvm/include/llvm/CodeGen/TargetRegisterInfo.h

@@ -29,6 +29,7 @@
 #include "llvm/Support/Printable.h"
 #include <cassert>
 #include <cstdint>
+#include <set>
 
 namespace llvm {
 
@@ -955,6 +956,20 @@ class TargetRegisterInfo : public MCRegisterInfo {
   /// Returns a -1 terminated array of pressure set IDs.
   virtual const int *getRegUnitPressureSets(unsigned RegUnit) const = 0;
 
+  /// EXPERIMENTAL: return true if Reg belongs to a prio (FP) register class.
+  /// Add some target specific methods to increase precision in counting of
+  /// live FP/GPR regs.
+private:
+  mutable std::set<unsigned> PrioRegClasses;
+  void initializePrioRegClasses() const;
+public:
+  bool isPrioRC(unsigned RegClassID) const;
+  bool isPrioVirtReg(Register Reg, const MachineRegisterInfo *MRI) const;
+  virtual unsigned getRCCountFactor(unsigned RegClassID) const { return 1; }
+  virtual bool isGPRLoRC(unsigned RegClassID) const { return false; }
+  virtual bool isGPRHiRC(unsigned RegClassID) const { return false; }
+  virtual bool isGPRLoHiRC(unsigned RegClassID) const { return false; }
+
   /// Get the scale factor of spill weight for this register class.
   virtual float getSpillWeightScaleFactor(const TargetRegisterClass *RC) const;