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36 changes: 36 additions & 0 deletions llvm/lib/Target/RISCV/RISCVISelLowering.cpp
Original file line number Diff line number Diff line change
Expand Up @@ -15312,6 +15312,40 @@ static SDValue reverseZExtICmpCombine(SDNode *N, SelectionDAG &DAG,
return DAG.getNode(ISD::ZERO_EXTEND, DL, VT, Res);
}

static SDValue reduceANDOfAtomicLoad(SDNode *N,
TargetLowering::DAGCombinerInfo &DCI) {
SelectionDAG &DAG = DCI.DAG;
if (N->getOpcode() != ISD::AND)
return SDValue();

SDValue N0 = N->getOperand(0);
if (N0.getOpcode() != ISD::ATOMIC_LOAD)
return SDValue();
if (!N0.hasOneUse())
return SDValue();

AtomicSDNode *ALoad = cast<AtomicSDNode>(N0.getNode());
if (isStrongerThanMonotonic(ALoad->getSuccessOrdering()))
return SDValue();

EVT LoadedVT = ALoad->getMemoryVT();
ConstantSDNode *MaskConst = dyn_cast<ConstantSDNode>(N->getOperand(1));
if (!MaskConst)
return SDValue();
uint64_t Mask = MaskConst->getZExtValue();
uint64_t ExpectedMask = maskTrailingOnes<uint64_t>(LoadedVT.getSizeInBits());
if (Mask != ExpectedMask)
return SDValue();

SDValue ZextLoad = DAG.getAtomicLoad(
ISD::ZEXTLOAD, SDLoc(N), ALoad->getMemoryVT(), N->getValueType(0),
ALoad->getChain(), ALoad->getBasePtr(), ALoad->getMemOperand());
DCI.CombineTo(N, ZextLoad);
DAG.ReplaceAllUsesOfValueWith(SDValue(N0.getNode(), 1), ZextLoad.getValue(1));
DCI.recursivelyDeleteUnusedNodes(N0.getNode());
return SDValue(N, 0);
}

// Combines two comparison operation and logic operation to one selection
// operation(min, max) and logic operation. Returns new constructed Node if
// conditions for optimization are satisfied.
Expand Down Expand Up @@ -15346,6 +15380,8 @@ static SDValue performANDCombine(SDNode *N,
return V;
if (SDValue V = combineBinOpOfExtractToReduceTree(N, DAG, Subtarget))
return V;
if (SDValue V = reduceANDOfAtomicLoad(N, DCI))
return V;

if (DCI.isAfterLegalizeDAG())
if (SDValue V = combineDeMorganOfBoolean(N, DAG))
Expand Down
3 changes: 3 additions & 0 deletions llvm/lib/Target/RISCV/RISCVInstrInfoA.td
Original file line number Diff line number Diff line change
Expand Up @@ -167,6 +167,8 @@ class seq_cst_store<PatFrag base>
let Predicates = [HasAtomicLdSt] in {
def : LdPat<relaxed_load<atomic_load_asext_8>, LB>;
def : LdPat<relaxed_load<atomic_load_asext_16>, LH>;
def : LdPat<relaxed_load<atomic_load_zext_8>, LBU>;
def : LdPat<relaxed_load<atomic_load_zext_16>, LHU>;

def : StPat<relaxed_store<atomic_store_8>, SB, GPR, XLenVT>;
def : StPat<relaxed_store<atomic_store_16>, SH, GPR, XLenVT>;
Expand All @@ -179,6 +181,7 @@ let Predicates = [HasAtomicLdSt, IsRV32] in {

let Predicates = [HasAtomicLdSt, IsRV64] in {
def : LdPat<relaxed_load<atomic_load_asext_32>, LW>;
def : LdPat<relaxed_load<atomic_load_zext_32>, LWU>;
def : LdPat<relaxed_load<atomic_load_nonext_64>, LD, i64>;
def : StPat<relaxed_store<atomic_store_64>, SD, GPR, i64>;
}
Expand Down
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