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6 changes: 3 additions & 3 deletions mlir/lib/Interfaces/ControlFlowInterfaces.cpp
Original file line number Diff line number Diff line change
Expand Up @@ -120,7 +120,7 @@ verifyTypesAlongAllEdges(Operation *op, RegionBranchPoint sourcePoint,

TypeRange succInputsTypes = succ.getSuccessorInputs().getTypes();
if (sourceTypes->size() != succInputsTypes.size()) {
InFlightDiagnostic diag = op->emitOpError(" region control flow edge ");
InFlightDiagnostic diag = op->emitOpError("region control flow edge ");
return printRegionEdgeName(diag, sourcePoint, succ)
<< ": source has " << sourceTypes->size()
<< " operands, but target successor needs "
Expand All @@ -132,7 +132,7 @@ verifyTypesAlongAllEdges(Operation *op, RegionBranchPoint sourcePoint,
Type sourceType = std::get<0>(typesIdx.value());
Type inputType = std::get<1>(typesIdx.value());
if (!regionInterface.areTypesCompatible(sourceType, inputType)) {
InFlightDiagnostic diag = op->emitOpError(" along control flow edge ");
InFlightDiagnostic diag = op->emitOpError("along control flow edge ");
return printRegionEdgeName(diag, sourcePoint, succ)
<< ": source type #" << typesIdx.index() << " " << sourceType
<< " should match input type #" << typesIdx.index() << " "
Expand Down Expand Up @@ -202,7 +202,7 @@ LogicalResult detail::verifyTypesAlongControlFlowEdges(Operation *op) {
// types match with the first one.
if (!areTypesCompatible(regionReturnOperands->getTypes(),
terminatorOperands.getTypes())) {
InFlightDiagnostic diag = op->emitOpError(" along control flow edge");
InFlightDiagnostic diag = op->emitOpError("along control flow edge");
return printRegionEdgeName(diag, region, point)
<< " operands mismatch between return-like terminators";
}
Expand Down
6 changes: 3 additions & 3 deletions mlir/test/Dialect/SCF/invalid.mlir
Original file line number Diff line number Diff line change
Expand Up @@ -544,7 +544,7 @@ func.func @while_invalid_terminator() {

func.func @while_cross_region_type_mismatch() {
%true = arith.constant true
// expected-error@+1 {{'scf.while' op region control flow edge from Region #0 to Region #1: source has 0 operands, but target successor needs 1}}
// expected-error@+1 {{'scf.while' op region control flow edge from Region #0 to Region #1: source has 0 operands, but target successor needs 1}}
scf.while : () -> () {
scf.condition(%true)
} do {
Expand All @@ -557,7 +557,7 @@ func.func @while_cross_region_type_mismatch() {

func.func @while_cross_region_type_mismatch() {
%true = arith.constant true
// expected-error@+1 {{'scf.while' op along control flow edge from Region #0 to Region #1: source type #0 'i1' should match input type #0 'i32'}}
// expected-error@+1 {{'scf.while' op along control flow edge from Region #0 to Region #1: source type #0 'i1' should match input type #0 'i32'}}
%0 = scf.while : () -> (i1) {
scf.condition(%true) %true : i1
} do {
Expand All @@ -570,7 +570,7 @@ func.func @while_cross_region_type_mismatch() {

func.func @while_result_type_mismatch() {
%true = arith.constant true
// expected-error@+1 {{'scf.while' op region control flow edge from Region #0 to parent results: source has 1 operands, but target successor needs 0}}
// expected-error@+1 {{'scf.while' op region control flow edge from Region #0 to parent results: source has 1 operands, but target successor needs 0}}
scf.while : () -> () {
scf.condition(%true) %true : i1
} do {
Expand Down
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