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[RISCV] Make xrivosvizip interleave2 and deinterleave2 undef safe #136733

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Merged
merged 2 commits into from
Apr 24, 2025
Merged

[RISCV] Make xrivosvizip interleave2 and deinterleave2 undef safe #136733

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bca81fa
[RISCV] Make xrivosvizip interleave2 and deinterleave2 undef safe
preames Apr 22, 2025
c23146f
Update llvm/lib/Target/RISCV/RISCVISelLowering.cpp
preames Apr 24, 2025
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10 changes: 8 additions & 2 deletions llvm/lib/Target/RISCV/RISCVISelLowering.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -11543,6 +11543,8 @@ SDValue RISCVTargetLowering::lowerVECTOR_DEINTERLEAVE(SDValue Op,
EVT NewVT = VT.getDoubleNumVectorElementsVT();
SDValue ZeroIdx = DAG.getVectorIdxConstant(0, DL);
Src = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, NewVT, Src, ZeroIdx);
// Freeze the source so we can increase its use count.
Src = DAG.getFreeze(Src);
SDValue Even = lowerVZIP(RISCVISD::RI_VUNZIP2A_VL, Src,
DAG.getUNDEF(NewVT), DL, DAG, Subtarget);
SDValue Odd = lowerVZIP(RISCVISD::RI_VUNZIP2B_VL, Src,
Expand All @@ -11552,6 +11554,9 @@ SDValue RISCVTargetLowering::lowerVECTOR_DEINTERLEAVE(SDValue Op,
return DAG.getMergeValues({Even, Odd}, DL);
}

// Freeze the sources so we can increase their use count.
V1 = DAG.getFreeze(V1);
V2 = DAG.getFreeze(V2);
SDValue Even =
lowerVZIP(RISCVISD::RI_VUNZIP2A_VL, V1, V2, DL, DAG, Subtarget);
SDValue Odd =
Expand Down Expand Up @@ -11793,8 +11798,9 @@ SDValue RISCVTargetLowering::lowerVECTOR_INTERLEAVE(SDValue Op,
// TODO: Figure out the best lowering for the spread variants
if (Subtarget.hasVendorXRivosVizip() && !Op.getOperand(0).isUndef() &&
!Op.getOperand(1).isUndef()) {
SDValue V1 = Op->getOperand(0);
SDValue V2 = Op->getOperand(1);
// Freeze the sources so we can increase their use count.
SDValue V1 = DAG.getFreeze(Op->getOperand(0));
SDValue V2 = DAG.getFreeze(Op->getOperand(1));
SDValue Lo = lowerVZIP(RISCVISD::RI_VZIP2A_VL, V1, V2, DL, DAG, Subtarget);
SDValue Hi = lowerVZIP(RISCVISD::RI_VZIP2B_VL, V1, V2, DL, DAG, Subtarget);
return DAG.getMergeValues({Lo, Hi}, DL);
Expand Down
16 changes: 8 additions & 8 deletions llvm/test/CodeGen/RISCV/rvv/vector-interleave.ll
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Expand Up @@ -260,18 +260,18 @@ define <vscale x 128 x i1> @vector_interleave_nxv128i1_nxv64i1(<vscale x 64 x i1
; ZIP-NEXT: vsetvli a0, zero, e8, m8, ta, ma
; ZIP-NEXT: vmv1r.v v9, v0
; ZIP-NEXT: vmv1r.v v0, v8
; ZIP-NEXT: vmv.v.i v24, 0
; ZIP-NEXT: vmerge.vim v16, v24, 1, v0
; ZIP-NEXT: vmv.v.i v16, 0
; ZIP-NEXT: vmerge.vim v24, v16, 1, v0
; ZIP-NEXT: vmv1r.v v0, v9
; ZIP-NEXT: vmerge.vim v8, v24, 1, v0
; ZIP-NEXT: vmerge.vim v8, v16, 1, v0
; ZIP-NEXT: vsetvli a0, zero, e8, m4, ta, ma
; ZIP-NEXT: ri.vzip2b.vv v4, v8, v16
; ZIP-NEXT: ri.vzip2b.vv v28, v12, v20
; ZIP-NEXT: ri.vzip2a.vv v0, v8, v16
; ZIP-NEXT: ri.vzip2a.vv v24, v12, v20
; ZIP-NEXT: ri.vzip2b.vv v4, v8, v24
; ZIP-NEXT: ri.vzip2b.vv v20, v12, v28
; ZIP-NEXT: ri.vzip2a.vv v0, v8, v24
; ZIP-NEXT: ri.vzip2a.vv v16, v12, v28
; ZIP-NEXT: vsetvli a0, zero, e8, m8, ta, ma
; ZIP-NEXT: vmsne.vi v9, v0, 0
; ZIP-NEXT: vmsne.vi v8, v24, 0
; ZIP-NEXT: vmsne.vi v8, v16, 0
; ZIP-NEXT: vmv1r.v v0, v9
; ZIP-NEXT: ret
%res = call <vscale x 128 x i1> @llvm.vector.interleave2.nxv128i1(<vscale x 64 x i1> %a, <vscale x 64 x i1> %b)
Expand Down
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