Skip to content
Merged
Changes from all commits
Commits
File filter

Filter by extension

Filter by extension

Conversations
Failed to load comments.
Loading
Jump to
Jump to file
Failed to load files.
Loading
Diff view
Diff view
20 changes: 13 additions & 7 deletions llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCCodeEmitter.cpp
Original file line number Diff line number Diff line change
Expand Up @@ -647,13 +647,15 @@ void AMDGPUMCCodeEmitter::getMachineOpValueT16Lo128(
void AMDGPUMCCodeEmitter::getMachineOpValueCommon(
const MCInst &MI, const MCOperand &MO, unsigned OpNo, APInt &Op,
SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const {
bool isLikeImm = false;
int64_t Val;
if (MO.isExpr() && MO.getExpr()->evaluateAsAbsolute(Val)) {
Op = Val;
return;
}

if (MO.isExpr() && MO.getExpr()->getKind() != MCExpr::Constant) {
if (MO.isImm()) {
Val = MO.getImm();
isLikeImm = true;
} else if (MO.isExpr() && MO.getExpr()->evaluateAsAbsolute(Val)) {
isLikeImm = true;
} else if (MO.isExpr()) {
// FIXME: If this is expression is PCRel or not should not depend on what
// the expression looks like. Given that this is just a general expression,
// it should probably be FK_Data_4 and whatever is producing
Expand Down Expand Up @@ -683,8 +685,12 @@ void AMDGPUMCCodeEmitter::getMachineOpValueCommon(
Op = *Enc;
return;
}
} else if (MO.isImm()) {
Op = MO.getImm();

llvm_unreachable("Operand not supported for SISrc");
}

if (isLikeImm) {
Op = Val;
return;
}

Expand Down
Loading