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[NFC] [AArch64] Simplify offset scaling in ldst-opt #137044

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Merged
merged 1 commit into from
Apr 23, 2025
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[NFC] [AArch64] Simplify offset scaling in ldst-opt #137044

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11 changes: 5 additions & 6 deletions llvm/lib/Target/AArch64/AArch64LoadStoreOptimizer.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -892,11 +892,10 @@ AArch64LoadStoreOpt::mergeNarrowZeroStores(MachineBasicBlock::iterator I,
OffsetImm = IOffsetInBytes;

int NewOpcode = getMatchingWideOpcode(Opc);
bool FinalIsScaled = !TII->hasUnscaledLdStOffset(NewOpcode);

// Adjust final offset if the result opcode is a scaled store.
if (FinalIsScaled) {
int NewOffsetStride = FinalIsScaled ? TII->getMemScale(NewOpcode) : 1;
// Adjust final offset on scaled stores because the new instruction
// has a different scale.
if (!TII->hasUnscaledLdStOffset(NewOpcode)) {
int NewOffsetStride = TII->getMemScale(NewOpcode);
assert(((OffsetImm % NewOffsetStride) == 0) &&
"Offset should be a multiple of the store memory scale");
OffsetImm = OffsetImm / NewOffsetStride;
Expand All @@ -906,7 +905,7 @@ AArch64LoadStoreOpt::mergeNarrowZeroStores(MachineBasicBlock::iterator I,
DebugLoc DL = I->getDebugLoc();
MachineBasicBlock *MBB = I->getParent();
MachineInstrBuilder MIB;
MIB = BuildMI(*MBB, InsertionPoint, DL, TII->get(getMatchingWideOpcode(Opc)))
MIB = BuildMI(*MBB, InsertionPoint, DL, TII->get(NewOpcode))
.addReg(isNarrowStore(Opc) ? AArch64::WZR : AArch64::XZR)
.add(BaseRegOp)
.addImm(OffsetImm)
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