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[TableGen][GISel] Allow isTrivialOperatorNode to import patterns with isStore and a memory VT. #137080

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Merged
merged 1 commit into from
Apr 24, 2025
Merged

[TableGen][GISel] Allow isTrivialOperatorNode to import patterns with isStore and a memory VT. #137080

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4 changes: 0 additions & 4 deletions llvm/include/llvm/Target/TargetSelectionDAG.td
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Original file line number Diff line number Diff line change
Expand Up @@ -1324,25 +1324,21 @@ def truncstorei8 : PatFrag<(ops node:$val, node:$ptr),
(truncstore node:$val, node:$ptr)> {
let IsStore = true;
let MemoryVT = i8;
let IsTruncStore = true;
}
def truncstorei16 : PatFrag<(ops node:$val, node:$ptr),
(truncstore node:$val, node:$ptr)> {
let IsStore = true;
let MemoryVT = i16;
let IsTruncStore = true;
}
def truncstorei32 : PatFrag<(ops node:$val, node:$ptr),
(truncstore node:$val, node:$ptr)> {
let IsStore = true;
let MemoryVT = i32;
let IsTruncStore = true;
}
def truncstorei64 : PatFrag<(ops node:$val, node:$ptr),
(truncstore node:$val, node:$ptr)> {
let IsStore = true;
let MemoryVT = i64;
let IsTruncStore = true;
}
def truncstoref16 : PatFrag<(ops node:$val, node:$ptr),
(truncstore node:$val, node:$ptr)> {
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2 changes: 0 additions & 2 deletions llvm/lib/Target/AMDGPU/SIInstrInfo.td
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Expand Up @@ -544,14 +544,12 @@ def truncstorei8_glue : PatFrag<(ops node:$val, node:$ptr),
(truncstore_glue node:$val, node:$ptr)> {
let IsStore = 1;
let MemoryVT = i8;
let IsTruncStore = 1;
}

def truncstorei16_glue : PatFrag<(ops node:$val, node:$ptr),
(truncstore_glue node:$val, node:$ptr)> {
let IsStore = 1;
let MemoryVT = i16;
let IsTruncStore = 1;
}

let IsStore = 1, AddressSpaces = StoreAddress_local.AddrSpaces in {
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2 changes: 1 addition & 1 deletion llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.tbuffer.store.d16.ll
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Expand Up @@ -189,7 +189,7 @@ define amdgpu_kernel void @tbuffer_store_d16_xyz(<4 x i32> %rsrc, <4 x half> %da
; GFX12-PACKED-GISEL-NEXT: s_wait_kmcnt 0x0
; GFX12-PACKED-GISEL-NEXT: v_mov_b32_e32 v0, s6
; GFX12-PACKED-GISEL-NEXT: v_mov_b32_e32 v1, s7
; GFX12-PACKED-GISEL-NEXT: tbuffer_store_d16_format_xyzw v[0:1], off, s[0:3], null format:[BUF_FMT_10_10_10_2_SNORM]
; GFX12-PACKED-GISEL-NEXT: tbuffer_store_d16_format_xyz v[0:1], off, s[0:3], null format:[BUF_FMT_10_10_10_2_SNORM]
; GFX12-PACKED-GISEL-NEXT: s_endpgm
main_body:
%data_subvec = shufflevector <4 x half> %data, <4 x half> poison, <3 x i32> <i32 0, i32 1, i32 2>
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2 changes: 1 addition & 1 deletion llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.tbuffer.store.d16.ll
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Expand Up @@ -211,7 +211,7 @@ define amdgpu_kernel void @tbuffer_store_d16_xyz(<4 x i32> %rsrc, <4 x half> %da
; GFX12-PACKED-GISEL-NEXT: v_mov_b32_e32 v0, s8
; GFX12-PACKED-GISEL-NEXT: v_mov_b32_e32 v1, s9
; GFX12-PACKED-GISEL-NEXT: v_mov_b32_e32 v2, s10
; GFX12-PACKED-GISEL-NEXT: tbuffer_store_d16_format_xyzw v[0:1], v2, s[0:3], null format:[BUF_FMT_10_10_10_2_SNORM] idxen
; GFX12-PACKED-GISEL-NEXT: tbuffer_store_d16_format_xyz v[0:1], v2, s[0:3], null format:[BUF_FMT_10_10_10_2_SNORM] idxen
; GFX12-PACKED-GISEL-NEXT: s_endpgm
main_body:
%data_subvec = shufflevector <4 x half> %data, <4 x half> poison, <3 x i32> <i32 0, i32 1, i32 2>
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3 changes: 3 additions & 0 deletions llvm/utils/TableGen/GlobalISelEmitter.cpp
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Expand Up @@ -219,6 +219,9 @@ static Error isTrivialOperatorNode(const TreePatternNode &N) {
if (Predicate.isLoad() && Predicate.getMemoryVT())
continue;

if (Predicate.isStore() && Predicate.getMemoryVT())
continue;

if (Predicate.isLoad() || Predicate.isStore()) {
if (Predicate.isUnindexed())
continue;
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