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3 changes: 0 additions & 3 deletions llvm/include/llvm/CodeGen/SelectionDAGNodes.h
Original file line number Diff line number Diff line change
Expand Up @@ -2533,9 +2533,6 @@ class StoreSDNode : public LSBaseSDNode {
/// For integers this is the same as doing a TRUNCATE and storing the result.
/// For floats, it is the same as doing an FP_ROUND and storing the result.
bool isTruncatingStore() const { return StoreSDNodeBits.IsTruncating; }
void setTruncatingStore(bool Truncating) {
StoreSDNodeBits.IsTruncating = Truncating;
}

const SDValue &getValue() const { return getOperand(1); }
const SDValue &getBasePtr() const { return getOperand(2); }
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17 changes: 10 additions & 7 deletions llvm/lib/Target/PowerPC/PPCISelLowering.cpp
Original file line number Diff line number Diff line change
Expand Up @@ -16562,13 +16562,16 @@ SDValue PPCTargetLowering::PerformDAGCombine(SDNode *N,
MemVT.getSizeInBits());
SDValue Const64 = DAG.getConstant(Val64, dl, MVT::i64);

// DAG.getTruncStore() can't be used here because it doesn't accept
// the general (base + offset) addressing mode.
// So we use UpdateNodeOperands and setTruncatingStore instead.
DAG.UpdateNodeOperands(N, N->getOperand(0), Const64, N->getOperand(2),
N->getOperand(3));
cast<StoreSDNode>(N)->setTruncatingStore(true);
return SDValue(N, 0);
auto *ST = cast<StoreSDNode>(N);
SDValue NewST = DAG.getStore(ST->getChain(), dl, Const64,
ST->getBasePtr(), ST->getOffset(), MemVT,
ST->getMemOperand(), ST->getAddressingMode(),
/*IsTruncating=*/true);
// Note we use CombineTo here to prevent DAGCombine from visiting the
// new store which will change the constant by removing non-demanded bits.
return ST->isUnindexed()
? DCI.CombineTo(N, NewST, /*AddTo=*/false)
: DCI.CombineTo(N, NewST, NewST.getValue(1), /*AddTo=*/false);
}

// For little endian, VSX stores require generating xxswapd/lxvd2x.
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