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[RISCV] Fix Defs/Uses for SiFive CLIC Support #137724

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Merged
merged 1 commit into from
Apr 29, 2025
Merged

[RISCV] Fix Defs/Uses for SiFive CLIC Support #137724

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8 changes: 4 additions & 4 deletions llvm/lib/Target/RISCV/RISCVFrameLowering.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -293,7 +293,7 @@ static void emitSiFiveCLICPreemptibleSaves(MachineFunction &MF,

// Enable interrupts.
BuildMI(MBB, MBBI, DL, TII->get(RISCV::CSRRSI))
.addReg(RISCV::X0)
.addReg(RISCV::X0, RegState::Define)
.addImm(RISCVSysReg::mstatus)
.addImm(8)
.setMIFlag(MachineInstr::FrameSetup);
Expand All @@ -315,7 +315,7 @@ static void emitSiFiveCLICPreemptibleRestores(MachineFunction &MF,

// Disable interrupts.
BuildMI(MBB, MBBI, DL, TII->get(RISCV::CSRRCI))
.addReg(RISCV::X0)
.addReg(RISCV::X0, RegState::Define)
.addImm(RISCVSysReg::mstatus)
.addImm(8)
.setMIFlag(MachineInstr::FrameSetup);
Expand All @@ -324,12 +324,12 @@ static void emitSiFiveCLICPreemptibleRestores(MachineFunction &MF,
// in the function, they have already been restored once, so now have the
// value stored in `emitSiFiveCLICPreemptibleSaves`.
BuildMI(MBB, MBBI, DL, TII->get(RISCV::CSRRW))
.addReg(RISCV::X0)
.addReg(RISCV::X0, RegState::Define)
.addImm(RISCVSysReg::mepc)
.addReg(RISCV::X9, RegState::Kill)
.setMIFlag(MachineInstr::FrameSetup);
BuildMI(MBB, MBBI, DL, TII->get(RISCV::CSRRW))
.addReg(RISCV::X0)
.addReg(RISCV::X0, RegState::Define)
.addImm(RISCVSysReg::mcause)
.addReg(RISCV::X8, RegState::Kill)
.setMIFlag(MachineInstr::FrameSetup);
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3 changes: 0 additions & 3 deletions llvm/test/CodeGen/RISCV/sifive-interrupt-attr.ll
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Expand Up @@ -4,9 +4,6 @@
; RUN: llc -mtriple riscv64-unknown-elf -mattr=+experimental-xsfmclic -o - %s \
; RUN: -verify-machineinstrs | FileCheck %s --check-prefix=RV64

;; These are failing to verify.
; XFAIL: *

; Test Handling of the SiFive-CLIC interrupt attributes.
;
; "stack-swap" means that sp should be swapped into `sf.mscratchcsw`
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