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[RISCV] Implement codegen for XAndesPerf lea instructions #137925

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Merged
merged 6 commits into from
May 12, 2025
Merged

[RISCV] Implement codegen for XAndesPerf lea instructions #137925

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253317e
[RISCV] Implement codegen for XAndesPerf lea instructions
tclin914 Apr 17, 2025
ffb5d39
Make the patterns for Zba be multiclass/class that we can reuse it.
tclin914 Apr 30, 2025
1dea0f3
Reuse the patterns from Zba for XAndesPerf lea instructions
tclin914 Apr 30, 2025
9fb0458
indent the body in multiclass by 2 spaces.
tclin914 May 1, 2025
15980a1
Switch the position of rs1 and rs2 for lea instruction
tclin914 May 2, 2025
4d20459
Change the order of rs1 and rs1 in ins rather than in argstr
tclin914 May 7, 2025
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14 changes: 10 additions & 4 deletions llvm/lib/Target/RISCV/RISCVInstrInfoXAndes.td
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Original file line number Diff line number Diff line change
Expand Up @@ -125,19 +125,25 @@ class NDSRVInstBFO<bits<3> funct3, string opcodestr>
let mayStore = 0;
}

class NDSRVInstRR<bits<7> funct7, string opcodestr,
string argstr = "$rd, $rs1, $rs2">
class NDSRVInstRR<bits<7> funct7, string opcodestr>
: RVInstR<funct7, 0b000, OPC_CUSTOM_2,
(outs GPR:$rd), (ins GPR:$rs1, GPR:$rs2),
opcodestr, argstr>,
opcodestr, "$rd, $rs1, $rs2">,
Sched<[WriteIALU, ReadIALU, ReadIALU]> {
let hasSideEffects = 0;
let mayLoad = 0;
let mayStore = 0;
}

class NDSRVInstLEA<bits<7> funct7, string opcodestr>
: NDSRVInstRR<funct7, opcodestr, "$rd, $rs2, $rs1">;
: RVInstR<funct7, 0b000, OPC_CUSTOM_2,
(outs GPR:$rd), (ins GPR:$rs2, GPR:$rs1),
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@topperc topperc May 9, 2025

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Please add a comment about why the operands are reversed.

opcodestr, "$rd, $rs1, $rs2">,
Sched<[WriteIALU, ReadIALU, ReadIALU]> {
let hasSideEffects = 0;
let mayLoad = 0;
let mayStore = 0;
}

// GP: ADDI, LB, LBU
class NDSRVInstLBGP<bits<2> funct2, string opcodestr>
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