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[RISCV] Implement codegen for XAndesPerf lea instructions #137925

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Merged
merged 6 commits into from
May 12, 2025
Merged

[RISCV] Implement codegen for XAndesPerf lea instructions #137925

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253317e
[RISCV] Implement codegen for XAndesPerf lea instructions
tclin914 Apr 17, 2025
ffb5d39
Make the patterns for Zba be multiclass/class that we can reuse it.
tclin914 Apr 30, 2025
1dea0f3
Reuse the patterns from Zba for XAndesPerf lea instructions
tclin914 Apr 30, 2025
9fb0458
indent the body in multiclass by 2 spaces.
tclin914 May 1, 2025
15980a1
Switch the position of rs1 and rs2 for lea instruction
tclin914 May 2, 2025
4d20459
Change the order of rs1 and rs1 in ins rather than in argstr
tclin914 May 7, 2025
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25 changes: 25 additions & 0 deletions llvm/lib/Target/RISCV/RISCVInstrInfoXAndes.td
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Original file line number Diff line number Diff line change
Expand Up @@ -356,3 +356,28 @@ def NDS_LDGP : NDSRVInstLDGP<0b011, "nds.ldgp">;
def NDS_SDGP : NDSRVInstSDGP<0b111, "nds.sdgp">;
} // Predicates = [HasVendorXAndesPerf, IsRV64]
} // DecoderNamespace = "XAndes"

// Patterns

let Predicates = [HasVendorXAndesPerf] in {
class NDS_LEAPat<int shamt, RVInstR Inst>
: Pat<(add (XLenVT GPR:$rs1), (shl GPR:$rs2, (XLenVT shamt))),
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@topperc topperc Apr 30, 2025

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You probably want to use add_like_non_imm12 instead of add. That's what we do for sh1add/sh2add/sh3add from Zba. That will handle or disjoint and prevent using the instruction if an ADDI could be used.

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@tclin914 tclin914 Apr 30, 2025

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Thanks for pointing that out. I've updated the patterns for Zba to be multiclass/class so they can be reused.

(Inst GPR:$rs1, GPR:$rs2)>;

def : NDS_LEAPat<1, NDS_LEA_H>;
def : NDS_LEAPat<2, NDS_LEA_W>;
def : NDS_LEAPat<3, NDS_LEA_D>;
} // Predicates = [HasVendorXAndesPerf]

let Predicates = [HasVendorXAndesPerf, IsRV64] in {
def : Pat<(add (XLenVT GPR:$rs1), (zexti32 (i64 GPR:$rs2))),
(NDS_LEA_B_ZE GPR:$rs1, GPR:$rs2)>;

class NDS_LEA_ZEPat<int shamt, RVInstR Inst>
: Pat<(add GPR:$rs1, (shl (zexti32 (XLenVT GPR:$rs2)), (XLenVT shamt))),
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@topperc topperc Apr 30, 2025

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I don't think you want zexti32 here. That will use this form if an AND is present or if the upper 32 bits are known to be 0. You probably only want the AND case. Use (and GPR:$rs2, 0xFFFFFFFF) like we do for sh1add/sh2add/sh3add.

(Inst GPR:$rs1, GPR:$rs2)>;

def : NDS_LEA_ZEPat<1, NDS_LEA_H_ZE>;
def : NDS_LEA_ZEPat<2, NDS_LEA_W_ZE>;
def : NDS_LEA_ZEPat<3, NDS_LEA_D_ZE>;
} // Predicates = [HasVendorXAndesPerf, IsRV64]
33 changes: 33 additions & 0 deletions llvm/test/CodeGen/RISCV/rv32xandesperf.ll
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@@ -0,0 +1,33 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -O0 -mtriple=riscv32 -mattr=+xandesperf -verify-machineinstrs < %s \
; RUN: | FileCheck %s

define i32 @lea_h(i32 %a, i32 %b) {
; CHECK-LABEL: lea_h:
; CHECK: # %bb.0:
; CHECK-NEXT: nds.lea.h a0, a0, a1
; CHECK-NEXT: ret
%shl = shl i32 %b, 1
%ret = add i32 %a, %shl
ret i32 %ret
}

define i32 @lea_w(i32 %a, i32 %b) {
; CHECK-LABEL: lea_w:
; CHECK: # %bb.0:
; CHECK-NEXT: nds.lea.w a0, a0, a1
; CHECK-NEXT: ret
%shl = shl i32 %b, 2
%ret = add i32 %a, %shl
ret i32 %ret
}

define i32 @lea_d(i32 %a, i32 %b) {
; CHECK-LABEL: lea_d:
; CHECK: # %bb.0:
; CHECK-NEXT: nds.lea.d a0, a0, a1
; CHECK-NEXT: ret
%shl = shl i32 %b, 3
%ret = add i32 %a, %shl
ret i32 %ret
}
46 changes: 46 additions & 0 deletions llvm/test/CodeGen/RISCV/rv64xandesperf.ll
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@@ -0,0 +1,46 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv64 -mattr=+xandesperf -verify-machineinstrs < %s \
; RUN: | FileCheck %s

define i64 @lea_b_ze(i32 %a, i64 %b) {
; CHECK-LABEL: lea_b_ze:
; CHECK: # %bb.0:
; CHECK-NEXT: nds.lea.b.ze a0, a1, a0
; CHECK-NEXT: ret
%conv = zext i32 %a to i64
%add = add i64 %conv, %b
ret i64 %add
}

define i64 @lea_h_ze(i32 %a, i64 %b) {
; CHECK-LABEL: lea_h_ze:
; CHECK: # %bb.0:
; CHECK-NEXT: nds.lea.h.ze a0, a1, a0
; CHECK-NEXT: ret
%conv = zext i32 %a to i64
%shl = shl nuw nsw i64 %conv, 1
%add = add i64 %shl, %b
ret i64 %add
}

define i64 @lea_w_ze(i32 %a, i64 %b) {
; CHECK-LABEL: lea_w_ze:
; CHECK: # %bb.0:
; CHECK-NEXT: nds.lea.w.ze a0, a1, a0
; CHECK-NEXT: ret
%conv = zext i32 %a to i64
%shl = shl nuw nsw i64 %conv, 2
%add = add i64 %shl, %b
ret i64 %add
}

define i64 @lea_d_ze(i32 %a, i64 %b) {
; CHECK-LABEL: lea_d_ze:
; CHECK: # %bb.0:
; CHECK-NEXT: nds.lea.d.ze a0, a1, a0
; CHECK-NEXT: ret
%conv = zext i32 %a to i64
%shl = shl nuw nsw i64 %conv, 3
%add = add i64 %shl, %b
ret i64 %add
}
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