Skip to content

[RISCV][MC] Support Base P non-GPR pair instructions #137927

New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Merged
merged 8 commits into from
Jun 30, 2025
Merged

[RISCV][MC] Support Base P non-GPR pair instructions #137927

Show file tree
Hide file tree
Changes from 1 commit
Commits
Show all changes
8 commits
Select commit Hold shift + click to select a range
a39ef92
[RISCV][MC] Support Base P non-GPR pair instructions
realqhc Apr 30, 2025
43d5b23
remove unused patterns, revert unnecessary change in rv64p-valid.s
realqhc Apr 30, 2025
82921ce
rename RVPUnaryImm9 to RVPUnaryImm10 and fix simm10 encoding, fix REV…
realqhc May 22, 2025
0d5b680
Change simm10 to simm10_unsigned to handle extended range for PLUI
realqhc May 22, 2025
fa5dd24
simplify RVPUnary#
realqhc May 30, 2025
7cd6711
Add back SImm10 for non-u load instructions. Add a test showing plui.…
realqhc Jun 6, 2025
94e492d
fix test to correctly handle difference between asm and obj output
realqhc Jun 20, 2025
1762fa3
Merge branch 'main' into p-no-gpr-pair
realqhc Jun 30, 2025
File filter

Filter by extension

Filter by extension
Conversations
Failed to load comments.
Loading
Jump to
Jump to file
Failed to load files.
Loading
Diff view
Diff view
4 changes: 4 additions & 0 deletions llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -809,6 +809,7 @@ struct RISCVOperand final : public MCParsedAsmOperand {

bool isSImm5() const { return isSImm<5>(); }
bool isSImm6() const { return isSImm<6>(); }
bool isSImm10() const { return isSImm<10>(); }
bool isSImm11() const { return isSImm<11>(); }
bool isSImm16() const { return isSImm<16>(); }
bool isSImm26() const { return isSImm<26>(); }
Expand Down Expand Up @@ -1540,6 +1541,9 @@ bool RISCVAsmParser::matchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
return generateImmOutOfRangeError(
Operands, ErrorInfo, 0, (1 << 9) - 8,
"immediate must be a multiple of 8 bytes in the range");
case Match_InvalidSImm10:
return generateImmOutOfRangeError(Operands, ErrorInfo, -(1 << 9),
(1 << 9) - 1);
case Match_InvalidSImm10Unsigned:
return generateImmOutOfRangeError(Operands, ErrorInfo, -(1 << 9),
(1 << 10) - 1);
Expand Down
1 change: 1 addition & 0 deletions llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -336,6 +336,7 @@ enum OperandType : unsigned {
OPERAND_SIMM5_PLUS1,
OPERAND_SIMM6,
OPERAND_SIMM6_NONZERO,
OPERAND_SIMM10,
OPERAND_SIMM10_UNSIGNED,
OPERAND_SIMM10_LSB0000_NONZERO,
OPERAND_SIMM11,
Expand Down
20 changes: 11 additions & 9 deletions llvm/lib/Target/RISCV/RISCVInstrInfoP.td
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -18,6 +18,8 @@
// Operand and SDNode transformation definitions.
//===----------------------------------------------------------------------===//

def simm10 : RISCVSImmLeafOp<10>;

// A 10-bit signed immediate allowing range [-512, 1023]
// but will decode to [-512, 511].
def simm10_unsigned : RISCVOp {
Expand All @@ -38,14 +40,15 @@ def simm10_unsigned : RISCVOp {
//===----------------------------------------------------------------------===//

let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
class RVPUnaryImm10<bits<7> funct7, string opcodestr>
: RVInstIBase<0b010, OPC_OP_IMM_32, (outs GPR:$rd), (ins simm10_unsigned:$simm10u),
opcodestr, "$rd, $simm10u"> {
bits<10> simm10u;
class RVPUnaryImm10<bits<7> funct7, string opcodestr,
DAGOperand TyImm10 = simm10>
: RVInstIBase<0b010, OPC_OP_IMM_32, (outs GPR:$rd), (ins TyImm10:$imm10),
opcodestr, "$rd, $imm10"> {
bits<10> imm10;

let Inst{31-25} = funct7;
let Inst{24-16} = simm10u{8-0};
let Inst{15} = simm10u{9};
let Inst{24-16} = imm10{8-0};
let Inst{15} = imm10{9};
}

let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
Expand Down Expand Up @@ -155,7 +158,6 @@ def PSEXT_W_H : RVPUnaryWUF<0b01, 0b00101, "psext.w.h">;
} // Predicates = [HasStdExtP, IsRV64]

let Predicates = [HasStdExtP] in
def PLUI_H : RVPUnaryImm10<0b1111000, "plui.h">;
def PLUI_H : RVPUnaryImm10<0b1111000, "plui.h", simm10_unsigned>;
let Predicates = [HasStdExtP, IsRV64] in
def PLUI_W : RVPUnaryImm10<0b1111001, "plui.w">;

def PLUI_W : RVPUnaryImm10<0b1111001, "plui.w", simm10_unsigned>;
2 changes: 2 additions & 0 deletions llvm/test/MC/RISCV/rv32p-invalid.s
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -3,6 +3,8 @@

# Imm overflow
pli.h a0, 0x400
# CHECK-ERROR: immediate must be an integer in the range [-512, 511]
plui.h a1, 0x400
# CHECK-ERROR: immediate must be an integer in the range [-512, 1023]
pli.b a0, 0x200
# CHECK-ERROR: immediate must be an integer in the range [0, 255]
Expand Down
5 changes: 4 additions & 1 deletion llvm/test/MC/RISCV/rv32p-valid.s
View file
Open in desktop
Original file line number Diff line number Diff line change
@@ -1,5 +1,5 @@
# RUN: llvm-mc %s -triple=riscv32 -mattr=+experimental-p -M no-aliases -show-encoding \
# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
# RUN: | FileCheck -check-prefixes=CHECK-ASM %s
Copy link
Collaborator

@topperc topperc Jun 6, 2025

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

Please add back CHECK-ASM-AND-OBJ. Add a additional CHECK-OBJ to the other RUN line that uses CHECK-ASM-AND-OBJ. Then use CHECK-ASM and CHECK-OBJ to show the different output for the case that fails.

# RUN: llvm-mc -filetype=obj -triple=riscv32 -mattr=+experimental-p < %s \
# RUN: | llvm-objdump --mattr=+experimental-p -M no-aliases -d -r --no-print-imm-hex - \
# RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s
Expand Down Expand Up @@ -73,3 +73,6 @@ psabs.b t0, t1
# CHECK-ASM-AND-OBJ: plui.h gp, 32
# CHECK-ASM: encoding: [0x9b,0x21,0x20,0xf0]
plui.h gp, 32
# CHECK-ASM-AND-OBJ: plui.h gp, -412
# CHECK-ASM: encoding: [0x9b,0xa1,0x64,0xf0]
plui.h gp, 612
4 changes: 3 additions & 1 deletion llvm/test/MC/RISCV/rv64p-invalid.s
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -3,9 +3,11 @@

# Imm overflow
pli.h a0, 0x400
# CHECK-ERROR: immediate must be an integer in the range [-512, 511]
plui.h a1, 0x400
# CHECK-ERROR: immediate must be an integer in the range [-512, 1023]
pli.w a1, -0x201
# CHECK-ERROR: immediate must be an integer in the range [-512, 1023]
# CHECK-ERROR: immediate must be an integer in the range [-512, 511]

pslli.b a6, a7, 100
# CHECK-ERROR: immediate must be an integer in the range [0, 7]
Expand Down
8 changes: 7 additions & 1 deletion llvm/test/MC/RISCV/rv64p-valid.s
View file
Open in desktop
Original file line number Diff line number Diff line change
@@ -1,5 +1,5 @@
# RUN: llvm-mc %s -triple=riscv64 -mattr=+experimental-p -M no-aliases -show-encoding \
# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
# RUN: | FileCheck -check-prefixes=CHECK-ASM %s
# RUN: llvm-mc -filetype=obj --triple=riscv64 -mattr=+experimental-p < %s \
# RUN: | llvm-objdump --triple=riscv64 --mattr=+experimental-p -M no-aliases --no-print-imm-hex -d -r - \
# RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s
Expand Down Expand Up @@ -97,6 +97,12 @@ psabs.b a0, s2
# CHECK-ASM-AND-OBJ: plui.h s2, 4
# CHECK-ASM: encoding: [0x1b,0x29,0x04,0xf0]
plui.h s2, 4
# CHECK-ASM-AND-OBJ: plui.h gp, -412
# CHECK-ASM: encoding: [0x9b,0xa1,0x64,0xf0]
plui.h gp, 612
# CHECK-ASM-AND-OBJ: plui.w a2, 1
# CHECK-ASM: encoding: [0x1b,0x26,0x01,0xf2]
plui.w a2, 1
# CHECK-ASM-AND-OBJ: plui.w a2, -1
# CHECK-ASM: encoding: [0x1b,0xa6,0xff,0xf3]
plui.w a2, 1023
Loading