Skip to content

[GlobalISel][AArch64] Handles bitreverse to prevent falling back #138150

New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Merged
merged 1 commit into from
May 6, 2025
Merged

[GlobalISel][AArch64] Handles bitreverse to prevent falling back #138150

Show file tree
Hide file tree
Changes from all commits
Commits
Show all changes
1 commit
Select commit
File filter

Filter by extension

Filter by extension
Conversations
Failed to load comments.
Loading
Jump to
Jump to file
Failed to load files.
Loading
Diff view
Diff view
1 change: 1 addition & 0 deletions llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -6139,6 +6139,7 @@ LegalizerHelper::moreElementsVector(MachineInstr &MI, unsigned TypeIdx,
case TargetOpcode::G_INTRINSIC_ROUND:
case TargetOpcode::G_INTRINSIC_ROUNDEVEN:
case TargetOpcode::G_INTRINSIC_TRUNC:
case TargetOpcode::G_BITREVERSE:
case TargetOpcode::G_BSWAP:
case TargetOpcode::G_FCANONICALIZE:
case TargetOpcode::G_SEXT_INREG:
Expand Down
2 changes: 2 additions & 0 deletions llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -366,6 +366,8 @@ AArch64LegalizerInfo::AArch64LegalizerInfo(const AArch64Subtarget &ST)
.legalFor({s32, s64, v8s8, v16s8})
.widenScalarToNextPow2(0, /*Min = */ 32)
.clampScalar(0, s32, s64)
.clampNumElements(0, v8s8, v16s8)
.moreElementsToNextPow2(0)
.lower();

getActionDefinitionsBuilder(G_BSWAP)
Expand Down
44 changes: 44 additions & 0 deletions llvm/test/CodeGen/AArch64/bitreverse.ll
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -136,6 +136,50 @@ define <16 x i8> @g_vec_16x8(<16 x i8> %a) {
ret <16 x i8> %b
}

declare <32 x i8> @llvm.bitreverse.v32i8(<32 x i8>) readnone

define <32 x i8> @g_vec_32x8(<32 x i8> %a) {
; CHECK-LABEL: g_vec_32x8:
; CHECK: // %bb.0:
; CHECK-NEXT: rbit v0.16b, v0.16b
; CHECK-NEXT: rbit v1.16b, v1.16b
; CHECK-NEXT: ret
%b = call <32 x i8> @llvm.bitreverse.v32i8(<32 x i8> %a)
ret <32 x i8> %b
}

declare <4 x i8> @llvm.bitreverse.v4i8(<4 x i8>) readnone

define <4 x i8> @g_vec_4x8(<4 x i8> %a) {
; SDAG-LABEL: g_vec_4x8:
; SDAG: // %bb.0:
; SDAG-NEXT: rev16 v0.8b, v0.8b
; SDAG-NEXT: rbit v0.8b, v0.8b
; SDAG-NEXT: ushr v0.4h, v0.4h, #8
; SDAG-NEXT: ret
;
; GISEL-LABEL: g_vec_4x8:
; GISEL: // %bb.0:
; GISEL-NEXT: uzp1 v0.8b, v0.8b, v0.8b
; GISEL-NEXT: rbit v0.8b, v0.8b
; GISEL-NEXT: ushll v0.8h, v0.8b, #0
; GISEL-NEXT: // kill: def $d0 killed $d0 killed $q0
; GISEL-NEXT: ret
%b = call <4 x i8> @llvm.bitreverse.v4i8(<4 x i8> %a)
ret <4 x i8> %b
}

declare <9 x i8> @llvm.bitreverse.v9i8(<9 x i8>) readnone

define <9 x i8> @g_vec_9x8(<9 x i8> %a) {
; CHECK-LABEL: g_vec_9x8:
; CHECK: // %bb.0:
; CHECK-NEXT: rbit v0.16b, v0.16b
; CHECK-NEXT: ret
%b = call <9 x i8> @llvm.bitreverse.v9i8(<9 x i8> %a)
ret <9 x i8> %b
}

declare <4 x i16> @llvm.bitreverse.v4i16(<4 x i16>) readnone

define <4 x i16> @g_vec_4x16(<4 x i16> %a) {
Expand Down
Loading