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[AArch64][SelectionDAG] Add support for 8to64 partial reduction cases #138269

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Merged
merged 4 commits into from
May 6, 2025
Merged

[AArch64][SelectionDAG] Add support for 8to64 partial reduction cases #138269

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3187e07
[AArch64][SelectionDAG] Add support for 8to64 partial reduction cases
NickGuy-Arm May 2, 2025
00371df
Switch to using wide adds instead of unpacking
NickGuy-Arm May 2, 2025
1d0994b
Address comments and add SVE2/SME guard & fallback
NickGuy-Arm May 2, 2025
466eb9f
Update doc-comment and add sme test run line
NickGuy-Arm May 6, 2025
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27 changes: 27 additions & 0 deletions llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -1867,6 +1867,8 @@ AArch64TargetLowering::AArch64TargetLowering(const TargetMachine &TM,
// Other pairs will default to 'Expand'.
setPartialReduceMLAAction(MVT::nxv2i64, MVT::nxv8i16, Legal);
setPartialReduceMLAAction(MVT::nxv4i32, MVT::nxv16i8, Legal);

setPartialReduceMLAAction(MVT::nxv2i64, MVT::nxv16i8, Custom);
}

// Handle operations that are only available in non-streaming SVE mode.
Expand Down Expand Up @@ -7767,6 +7769,9 @@ SDValue AArch64TargetLowering::LowerOperation(SDValue Op,
return LowerFLDEXP(Op, DAG);
case ISD::EXPERIMENTAL_VECTOR_HISTOGRAM:
return LowerVECTOR_HISTOGRAM(Op, DAG);
case ISD::PARTIAL_REDUCE_SMLA:
case ISD::PARTIAL_REDUCE_UMLA:
return LowerPARTIAL_REDUCE_MLA(Op, DAG);
}
}

Expand Down Expand Up @@ -29509,6 +29514,28 @@ SDValue AArch64TargetLowering::LowerVECTOR_HISTOGRAM(SDValue Op,
return Scatter;
}

SDValue
AArch64TargetLowering::LowerPARTIAL_REDUCE_MLA(SDValue Op,
SelectionDAG &DAG) const {
SDLoc DL(Op);

auto Acc = Op.getOperand(0);
auto LHS = Op.getOperand(1);
auto RHS = Op.getOperand(2);
auto ResultVT = Op.getValueType();
assert(ResultVT == MVT::nxv2i64 && LHS.getValueType() == MVT::nxv16i8);

EVT InputVT = MVT::nxv4i32;
SDValue DotNode = DAG.getNode(Op.getOpcode(), DL, InputVT,
DAG.getConstant(0, DL, InputVT), LHS, RHS);

bool IsUnsigned = Op.getOpcode() == ISD::PARTIAL_REDUCE_UMLA;
unsigned LoOpcode = IsUnsigned ? AArch64ISD::UADDWB : AArch64ISD::SADDWB;
unsigned HiOpcode = IsUnsigned ? AArch64ISD::UADDWT : AArch64ISD::SADDWT;
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@MacDue MacDue May 2, 2025

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You need to check Subtarget->hasSVE2() || Subtarget->isStreamingSVEAvailable() before using the wide adds IIRC. They're gated under if !IsFeatureImplemented(FEAT_SVE2) && !IsFeatureImplemented(FEAT_SME).

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@NickGuy-Arm NickGuy-Arm May 2, 2025

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I had that at first, but removed it as the PartialReduceMLAAction was only set if we had SVE, not realising that these instructions were specifically SVE2. Added, as well as a fallback to the old unpack/add approach for when we don't have SVE2.

SDValue Lo = DAG.getNode(LoOpcode, DL, ResultVT, Acc, DotNode);
return DAG.getNode(HiOpcode, DL, ResultVT, Lo, DotNode);
}

SDValue
AArch64TargetLowering::LowerFixedLengthFPToIntToSVE(SDValue Op,
SelectionDAG &DAG) const {
Expand Down
1 change: 1 addition & 0 deletions llvm/lib/Target/AArch64/AArch64ISelLowering.h
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Expand Up @@ -1181,6 +1181,7 @@ class AArch64TargetLowering : public TargetLowering {
SDValue LowerVECTOR_DEINTERLEAVE(SDValue Op, SelectionDAG &DAG) const;
SDValue LowerVECTOR_INTERLEAVE(SDValue Op, SelectionDAG &DAG) const;
SDValue LowerVECTOR_HISTOGRAM(SDValue Op, SelectionDAG &DAG) const;
SDValue LowerPARTIAL_REDUCE_MLA(SDValue Op, SelectionDAG &DAG) const;
SDValue LowerDIV(SDValue Op, SelectionDAG &DAG) const;
SDValue LowerMUL(SDValue Op, SelectionDAG &DAG) const;
SDValue LowerVectorSRA_SRL_SHL(SDValue Op, SelectionDAG &DAG) const;
Expand Down
82 changes: 8 additions & 74 deletions llvm/test/CodeGen/AArch64/sve-partial-reduce-dot-product.ll
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Expand Up @@ -198,43 +198,10 @@ define <vscale x 4 x i64> @udot_8to64(<vscale x 4 x i64> %acc, <vscale x 16 x i8
;
; CHECK-NEWLOWERING-LABEL: udot_8to64:
; CHECK-NEWLOWERING: // %bb.0: // %entry
; CHECK-NEWLOWERING-NEXT: uunpkhi z4.h, z2.b
; CHECK-NEWLOWERING-NEXT: uunpklo z2.h, z2.b
; CHECK-NEWLOWERING-NEXT: uunpkhi z5.h, z3.b
; CHECK-NEWLOWERING-NEXT: uunpklo z3.h, z3.b
; CHECK-NEWLOWERING-NEXT: ptrue p0.d
; CHECK-NEWLOWERING-NEXT: uunpklo z6.s, z4.h
; CHECK-NEWLOWERING-NEXT: uunpklo z7.s, z2.h
; CHECK-NEWLOWERING-NEXT: uunpklo z24.s, z5.h
; CHECK-NEWLOWERING-NEXT: uunpklo z25.s, z3.h
; CHECK-NEWLOWERING-NEXT: uunpkhi z4.s, z4.h
; CHECK-NEWLOWERING-NEXT: uunpkhi z2.s, z2.h
; CHECK-NEWLOWERING-NEXT: uunpkhi z5.s, z5.h
; CHECK-NEWLOWERING-NEXT: uunpkhi z3.s, z3.h
; CHECK-NEWLOWERING-NEXT: uunpklo z26.d, z6.s
; CHECK-NEWLOWERING-NEXT: uunpklo z27.d, z7.s
; CHECK-NEWLOWERING-NEXT: uunpklo z28.d, z24.s
; CHECK-NEWLOWERING-NEXT: uunpklo z29.d, z25.s
; CHECK-NEWLOWERING-NEXT: uunpkhi z6.d, z6.s
; CHECK-NEWLOWERING-NEXT: uunpkhi z7.d, z7.s
; CHECK-NEWLOWERING-NEXT: uunpkhi z24.d, z24.s
; CHECK-NEWLOWERING-NEXT: uunpkhi z25.d, z25.s
; CHECK-NEWLOWERING-NEXT: mla z1.d, p0/m, z26.d, z28.d
; CHECK-NEWLOWERING-NEXT: uunpklo z26.d, z4.s
; CHECK-NEWLOWERING-NEXT: uunpklo z28.d, z5.s
; CHECK-NEWLOWERING-NEXT: mla z0.d, p0/m, z27.d, z29.d
; CHECK-NEWLOWERING-NEXT: uunpklo z27.d, z2.s
; CHECK-NEWLOWERING-NEXT: uunpklo z29.d, z3.s
; CHECK-NEWLOWERING-NEXT: uunpkhi z4.d, z4.s
; CHECK-NEWLOWERING-NEXT: uunpkhi z2.d, z2.s
; CHECK-NEWLOWERING-NEXT: uunpkhi z5.d, z5.s
; CHECK-NEWLOWERING-NEXT: uunpkhi z3.d, z3.s
; CHECK-NEWLOWERING-NEXT: mla z1.d, p0/m, z6.d, z24.d
; CHECK-NEWLOWERING-NEXT: mla z0.d, p0/m, z7.d, z25.d
; CHECK-NEWLOWERING-NEXT: mla z1.d, p0/m, z26.d, z28.d
; CHECK-NEWLOWERING-NEXT: mla z0.d, p0/m, z27.d, z29.d
; CHECK-NEWLOWERING-NEXT: mla z1.d, p0/m, z4.d, z5.d
; CHECK-NEWLOWERING-NEXT: mla z0.d, p0/m, z2.d, z3.d
; CHECK-NEWLOWERING-NEXT: movi v4.2d, #0000000000000000
; CHECK-NEWLOWERING-NEXT: udot z4.s, z2.b, z3.b
; CHECK-NEWLOWERING-NEXT: uaddwb z0.d, z0.d, z4.s
; CHECK-NEWLOWERING-NEXT: uaddwt z0.d, z0.d, z4.s
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@huntergr-arm huntergr-arm May 2, 2025

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I'm wondering slightly about only updating half the accumulator (<vscale x 4 x i64> will be distributed across two registers), but I believe that's fine under the definition of a partial reduction. Certainly much nicer looking than the previous codegen.

; CHECK-NEWLOWERING-NEXT: ret
entry:
%a.wide = zext <vscale x 16 x i8> %a to <vscale x 16 x i64>
Expand All @@ -258,43 +225,10 @@ define <vscale x 4 x i64> @sdot_8to64(<vscale x 4 x i64> %acc, <vscale x 16 x i8
;
; CHECK-NEWLOWERING-LABEL: sdot_8to64:
; CHECK-NEWLOWERING: // %bb.0: // %entry
; CHECK-NEWLOWERING-NEXT: sunpkhi z4.h, z2.b
; CHECK-NEWLOWERING-NEXT: sunpklo z2.h, z2.b
; CHECK-NEWLOWERING-NEXT: sunpkhi z5.h, z3.b
; CHECK-NEWLOWERING-NEXT: sunpklo z3.h, z3.b
; CHECK-NEWLOWERING-NEXT: ptrue p0.d
; CHECK-NEWLOWERING-NEXT: sunpklo z6.s, z4.h
; CHECK-NEWLOWERING-NEXT: sunpklo z7.s, z2.h
; CHECK-NEWLOWERING-NEXT: sunpklo z24.s, z5.h
; CHECK-NEWLOWERING-NEXT: sunpklo z25.s, z3.h
; CHECK-NEWLOWERING-NEXT: sunpkhi z4.s, z4.h
; CHECK-NEWLOWERING-NEXT: sunpkhi z2.s, z2.h
; CHECK-NEWLOWERING-NEXT: sunpkhi z5.s, z5.h
; CHECK-NEWLOWERING-NEXT: sunpkhi z3.s, z3.h
; CHECK-NEWLOWERING-NEXT: sunpklo z26.d, z6.s
; CHECK-NEWLOWERING-NEXT: sunpklo z27.d, z7.s
; CHECK-NEWLOWERING-NEXT: sunpklo z28.d, z24.s
; CHECK-NEWLOWERING-NEXT: sunpklo z29.d, z25.s
; CHECK-NEWLOWERING-NEXT: sunpkhi z6.d, z6.s
; CHECK-NEWLOWERING-NEXT: sunpkhi z7.d, z7.s
; CHECK-NEWLOWERING-NEXT: sunpkhi z24.d, z24.s
; CHECK-NEWLOWERING-NEXT: sunpkhi z25.d, z25.s
; CHECK-NEWLOWERING-NEXT: mla z1.d, p0/m, z26.d, z28.d
; CHECK-NEWLOWERING-NEXT: sunpklo z26.d, z4.s
; CHECK-NEWLOWERING-NEXT: sunpklo z28.d, z5.s
; CHECK-NEWLOWERING-NEXT: mla z0.d, p0/m, z27.d, z29.d
; CHECK-NEWLOWERING-NEXT: sunpklo z27.d, z2.s
; CHECK-NEWLOWERING-NEXT: sunpklo z29.d, z3.s
; CHECK-NEWLOWERING-NEXT: sunpkhi z4.d, z4.s
; CHECK-NEWLOWERING-NEXT: sunpkhi z2.d, z2.s
; CHECK-NEWLOWERING-NEXT: sunpkhi z5.d, z5.s
; CHECK-NEWLOWERING-NEXT: sunpkhi z3.d, z3.s
; CHECK-NEWLOWERING-NEXT: mla z1.d, p0/m, z6.d, z24.d
; CHECK-NEWLOWERING-NEXT: mla z0.d, p0/m, z7.d, z25.d
; CHECK-NEWLOWERING-NEXT: mla z1.d, p0/m, z26.d, z28.d
; CHECK-NEWLOWERING-NEXT: mla z0.d, p0/m, z27.d, z29.d
; CHECK-NEWLOWERING-NEXT: mla z1.d, p0/m, z4.d, z5.d
; CHECK-NEWLOWERING-NEXT: mla z0.d, p0/m, z2.d, z3.d
; CHECK-NEWLOWERING-NEXT: movi v4.2d, #0000000000000000
; CHECK-NEWLOWERING-NEXT: sdot z4.s, z2.b, z3.b
; CHECK-NEWLOWERING-NEXT: saddwb z0.d, z0.d, z4.s
; CHECK-NEWLOWERING-NEXT: saddwt z0.d, z0.d, z4.s
; CHECK-NEWLOWERING-NEXT: ret
entry:
%a.wide = sext <vscale x 16 x i8> %a to <vscale x 16 x i64>
Expand Down