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merged 9 commits into from
May 29, 2025
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[SPARC][IAS] Add definitions for OSA 2011 instructions #138403

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[𝘀𝗽𝗿] changes to main this commit is based on
koachan May 3, 2025
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[𝘀𝗽𝗿] changes introduced through rebase
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Separate cryptographic instructions
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[𝘀𝗽𝗿] changes introduced through rebase
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[𝘀𝗽𝗿] changes introduced through rebase
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1 change: 1 addition & 0 deletions llvm/include/llvm/BinaryFormat/ELFRelocs/Sparc.def
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Expand Up @@ -87,3 +87,4 @@ ELF_RELOC(R_SPARC_GOTDATA_LOX10, 81)
ELF_RELOC(R_SPARC_GOTDATA_OP_HIX22, 82)
ELF_RELOC(R_SPARC_GOTDATA_OP_LOX10, 83)
ELF_RELOC(R_SPARC_GOTDATA_OP, 84)
ELF_RELOC(R_SPARC_WDISP10, 88)
9 changes: 9 additions & 0 deletions llvm/lib/Target/Sparc/Disassembler/SparcDisassembler.cpp
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Expand Up @@ -261,6 +261,8 @@ DecodeCoprocPairRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address,

static DecodeStatus DecodeCall(MCInst &Inst, unsigned insn, uint64_t Address,
const MCDisassembler *Decoder);
static DecodeStatus DecodeSIMM5(MCInst &Inst, unsigned insn, uint64_t Address,
const MCDisassembler *Decoder);
static DecodeStatus DecodeSIMM13(MCInst &Inst, unsigned insn, uint64_t Address,
const MCDisassembler *Decoder);

Expand Down Expand Up @@ -340,6 +342,13 @@ static DecodeStatus DecodeCall(MCInst &MI, unsigned insn, uint64_t Address,
return MCDisassembler::Success;
}

static DecodeStatus DecodeSIMM5(MCInst &MI, unsigned insn, uint64_t Address,
const MCDisassembler *Decoder) {
assert(isUInt<5>(insn));
MI.addOperand(MCOperand::createImm(SignExtend64<5>(insn)));
return MCDisassembler::Success;
}

static DecodeStatus DecodeSIMM13(MCInst &MI, unsigned insn, uint64_t Address,
const MCDisassembler *Decoder) {
assert(isUInt<13>(insn));
Expand Down
15 changes: 15 additions & 0 deletions llvm/lib/Target/Sparc/MCTargetDesc/SparcAsmBackend.cpp
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Expand Up @@ -50,6 +50,15 @@ static unsigned adjustFixupValue(unsigned Kind, uint64_t Value) {
return (d16hi << 20) | d16lo;
}

case Sparc::fixup_sparc_br10: {
// 7.17 Compare and Branch
// Inst{20-19} = d10hi;
// Inst{12-5} = d10lo;
unsigned d10hi = (Value >> 10) & 0x3;
unsigned d10lo = (Value >> 2) & 0xff;
return (d10hi << 19) | (d10lo << 5);
}

case Sparc::fixup_sparc_hix22:
return (~Value >> 10) & 0x3fffff;

Expand Down Expand Up @@ -162,11 +171,13 @@ namespace {

MCFixupKindInfo getFixupKindInfo(MCFixupKind Kind) const override {
const static MCFixupKindInfo InfosBE[Sparc::NumTargetFixupKinds] = {
// clang-format off
// name offset bits flags
{ "fixup_sparc_call30", 2, 30, MCFixupKindInfo::FKF_IsPCRel },
{ "fixup_sparc_br22", 10, 22, MCFixupKindInfo::FKF_IsPCRel },
{ "fixup_sparc_br19", 13, 19, MCFixupKindInfo::FKF_IsPCRel },
{ "fixup_sparc_br16", 0, 32, MCFixupKindInfo::FKF_IsPCRel },
{ "fixup_sparc_br10", 0, 32, MCFixupKindInfo::FKF_IsPCRel },
{ "fixup_sparc_13", 19, 13, 0 },
{ "fixup_sparc_hi22", 10, 22, 0 },
{ "fixup_sparc_lo10", 22, 10, 0 },
Expand Down Expand Up @@ -205,14 +216,17 @@ namespace {
{ "fixup_sparc_gotdata_hix22", 0, 0, 0 },
{ "fixup_sparc_gotdata_lox10", 0, 0, 0 },
{ "fixup_sparc_gotdata_op", 0, 0, 0 },
// clang-format on
};

const static MCFixupKindInfo InfosLE[Sparc::NumTargetFixupKinds] = {
// clang-format off
// name offset bits flags
{ "fixup_sparc_call30", 0, 30, MCFixupKindInfo::FKF_IsPCRel },
{ "fixup_sparc_br22", 0, 22, MCFixupKindInfo::FKF_IsPCRel },
{ "fixup_sparc_br19", 0, 19, MCFixupKindInfo::FKF_IsPCRel },
{ "fixup_sparc_br16", 32, 0, MCFixupKindInfo::FKF_IsPCRel },
{ "fixup_sparc_br10", 32, 0, MCFixupKindInfo::FKF_IsPCRel },
{ "fixup_sparc_13", 0, 13, 0 },
{ "fixup_sparc_hi22", 0, 22, 0 },
{ "fixup_sparc_lo10", 0, 10, 0 },
Expand Down Expand Up @@ -251,6 +265,7 @@ namespace {
{ "fixup_sparc_gotdata_hix22", 0, 0, 0 },
{ "fixup_sparc_gotdata_lox10", 0, 0, 0 },
{ "fixup_sparc_gotdata_op", 0, 0, 0 },
// clang-format on
};

// Fixup kinds from .reloc directive are like R_SPARC_NONE. They do
Expand Down
2 changes: 2 additions & 0 deletions llvm/lib/Target/Sparc/MCTargetDesc/SparcELFObjectWriter.cpp
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Expand Up @@ -84,6 +84,8 @@ unsigned SparcELFObjectWriter::getRelocType(MCContext &Ctx,
case Sparc::fixup_sparc_br19: return ELF::R_SPARC_WDISP19;
case Sparc::fixup_sparc_br16:
return ELF::R_SPARC_WDISP16;
case Sparc::fixup_sparc_br10:
return ELF::R_SPARC_WDISP10;
case Sparc::fixup_sparc_pc22: return ELF::R_SPARC_PC22;
case Sparc::fixup_sparc_pc10: return ELF::R_SPARC_PC10;
case Sparc::fixup_sparc_wplt30: return ELF::R_SPARC_WPLT30;
Expand Down
6 changes: 5 additions & 1 deletion llvm/lib/Target/Sparc/MCTargetDesc/SparcFixupKinds.h
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Expand Up @@ -11,6 +11,7 @@

#include "llvm/MC/MCFixup.h"

// clang-format off
namespace llvm {
namespace Sparc {
enum Fixups {
Expand All @@ -28,6 +29,9 @@ namespace llvm {
/// fixup_sparc_bpr - 16-bit fixup for bpr
fixup_sparc_br16,

/// fixup_sparc_br10 - 10-bit fixup for cbcond
fixup_sparc_br10,

/// fixup_sparc_13 - 13-bit fixup
fixup_sparc_13,

Expand Down Expand Up @@ -112,5 +116,5 @@ namespace llvm {
};
}
}

// clang-format on
#endif
4 changes: 2 additions & 2 deletions llvm/lib/Target/Sparc/MCTargetDesc/SparcInstPrinter.cpp
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Expand Up @@ -192,8 +192,8 @@ void SparcInstPrinter::printCCOperand(const MCInst *MI, int opNum,
// Make sure CC is a fp conditional flag.
CC = (CC < SPCC::FCC_BEGIN) ? (CC + SPCC::FCC_BEGIN) : CC;
break;
case SP::CBCOND:
case SP::CBCONDA:
case SP::CPBCOND:
case SP::CPBCONDA:
// Make sure CC is a cp conditional flag.
CC = (CC < SPCC::CPCC_BEGIN) ? (CC + SPCC::CPCC_BEGIN) : CC;
break;
Expand Down
39 changes: 39 additions & 0 deletions llvm/lib/Target/Sparc/MCTargetDesc/SparcMCCodeEmitter.cpp
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Expand Up @@ -71,6 +71,9 @@ class SparcMCCodeEmitter : public MCCodeEmitter {
unsigned getBranchTargetOpValue(const MCInst &MI, unsigned OpNo,
SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI) const;
unsigned getSImm5OpValue(const MCInst &MI, unsigned OpNo,
SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI) const;
unsigned getSImm13OpValue(const MCInst &MI, unsigned OpNo,
SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI) const;
Expand All @@ -80,6 +83,9 @@ class SparcMCCodeEmitter : public MCCodeEmitter {
unsigned getBranchOnRegTargetOpValue(const MCInst &MI, unsigned OpNo,
SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI) const;
unsigned getCompareAndBranchTargetOpValue(const MCInst &MI, unsigned OpNo,
SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI) const;
};

} // end anonymous namespace
Expand Down Expand Up @@ -141,6 +147,26 @@ getMachineOpValue(const MCInst &MI, const MCOperand &MO,
return 0;
}

unsigned SparcMCCodeEmitter::getSImm5OpValue(const MCInst &MI, unsigned OpNo,
SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI) const {
const MCOperand &MO = MI.getOperand(OpNo);

if (MO.isImm())
return MO.getImm();

assert(MO.isExpr() &&
"getSImm5OpValue expects only expressions or an immediate");

const MCExpr *Expr = MO.getExpr();

// Constant value, no fixup is needed
if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr))
return CE->getValue();

llvm_unreachable("simm5 operands can only be used with constants!");
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Shouldn't it be a R_SPARC_5 relocation?
EIther way, if this code is reachable, it shouldn't be llvm_unreachable.

}

unsigned
SparcMCCodeEmitter::getSImm13OpValue(const MCInst &MI, unsigned OpNo,
SmallVectorImpl<MCFixup> &Fixups,
Expand Down Expand Up @@ -239,6 +265,19 @@ getBranchOnRegTargetOpValue(const MCInst &MI, unsigned OpNo,
return 0;
}

unsigned SparcMCCodeEmitter::getCompareAndBranchTargetOpValue(
const MCInst &MI, unsigned OpNo, SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI) const {
const MCOperand &MO = MI.getOperand(OpNo);
if (MO.isReg() || MO.isImm())
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It can't be a register, can it?

return getMachineOpValue(MI, MO, Fixups, STI);

Fixups.push_back(
MCFixup::create(0, MO.getExpr(), (MCFixupKind)Sparc::fixup_sparc_br10));

return 0;
}

#include "SparcGenMCCodeEmitter.inc"

MCCodeEmitter *llvm::createSparcMCCodeEmitter(const MCInstrInfo &MCII,
Expand Down
19 changes: 15 additions & 4 deletions llvm/lib/Target/Sparc/Sparc.td
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Expand Up @@ -49,6 +49,15 @@ def FeatureVIS2
def FeatureVIS3
: SubtargetFeature<"vis3", "IsVIS3", "true",
"Enable Visual Instruction Set extensions III">;
def FeatureUA2005
: SubtargetFeature<"ua2005", "IsUA2005", "true",
"Enable UltraSPARC Architecture 2005 extensions">;
def FeatureUA2007
: SubtargetFeature<"ua2007", "IsUA2007", "true",
"Enable UltraSPARC Architecture 2007 extensions">;
def FeatureOSA2011
: SubtargetFeature<"osa2011", "IsOSA2011", "true",
"Enable Oracle SPARC Architecture 2011 extensions">;
def FeatureLeon
: SubtargetFeature<"leon", "IsLeon", "true",
"Enable LEON extensions">;
Expand Down Expand Up @@ -152,13 +161,15 @@ def : Proc<"ultrasparc3", [FeatureV9, FeatureV8Deprecated, FeatureVIS,
FeatureVIS2],
[TuneSlowRDPC]>;
def : Proc<"niagara", [FeatureV9, FeatureV8Deprecated, FeatureVIS,
FeatureVIS2]>;
FeatureVIS2, FeatureUA2005]>;
def : Proc<"niagara2", [FeatureV9, FeatureV8Deprecated, UsePopc,
FeatureVIS, FeatureVIS2]>;
FeatureVIS, FeatureVIS2, FeatureUA2005]>;
def : Proc<"niagara3", [FeatureV9, FeatureV8Deprecated, UsePopc,
FeatureVIS, FeatureVIS2]>;
FeatureVIS, FeatureVIS2, FeatureVIS3,
FeatureUA2005, FeatureUA2007]>;
def : Proc<"niagara4", [FeatureV9, FeatureV8Deprecated, UsePopc,
FeatureVIS, FeatureVIS2, FeatureVIS3]>;
FeatureVIS, FeatureVIS2, FeatureVIS3,
FeatureUA2005, FeatureUA2007, FeatureOSA2011]>;

// LEON 2 FT generic
def : Processor<"leon2", LEON2Itineraries,
Expand Down
30 changes: 3 additions & 27 deletions llvm/lib/Target/Sparc/SparcInstr64Bit.td
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Expand Up @@ -180,37 +180,13 @@ def : Pat<(i64 (ctpop i64:$src)), (POPCrr $src)>;
//===----------------------------------------------------------------------===//

let Predicates = [Is64Bit] in {

def MULXrr : F3_1<2, 0b001001,
(outs I64Regs:$rd), (ins I64Regs:$rs1, I64Regs:$rs2),
"mulx $rs1, $rs2, $rd",
[(set i64:$rd, (mul i64:$rs1, i64:$rs2))]>;
def MULXri : F3_2<2, 0b001001,
(outs IntRegs:$rd), (ins IntRegs:$rs1, i64imm:$simm13),
"mulx $rs1, $simm13, $rd",
[(set i64:$rd, (mul i64:$rs1, (i64 simm13:$simm13)))]>;
defm MULX : F3_12<"mulx", 0b001001, mul, I64Regs, i64, i64imm>;

// Division can trap.
let hasSideEffects = 1 in {
def SDIVXrr : F3_1<2, 0b101101,
(outs I64Regs:$rd), (ins I64Regs:$rs1, I64Regs:$rs2),
"sdivx $rs1, $rs2, $rd",
[(set i64:$rd, (sdiv i64:$rs1, i64:$rs2))]>;
def SDIVXri : F3_2<2, 0b101101,
(outs IntRegs:$rd), (ins IntRegs:$rs1, i64imm:$simm13),
"sdivx $rs1, $simm13, $rd",
[(set i64:$rd, (sdiv i64:$rs1, (i64 simm13:$simm13)))]>;

def UDIVXrr : F3_1<2, 0b001101,
(outs I64Regs:$rd), (ins I64Regs:$rs1, I64Regs:$rs2),
"udivx $rs1, $rs2, $rd",
[(set i64:$rd, (udiv i64:$rs1, i64:$rs2))]>;
def UDIVXri : F3_2<2, 0b001101,
(outs IntRegs:$rd), (ins IntRegs:$rs1, i64imm:$simm13),
"udivx $rs1, $simm13, $rd",
[(set i64:$rd, (udiv i64:$rs1, (i64 simm13:$simm13)))]>;
defm SDIVX : F3_12<"sdivx", 0b101101, sdiv, I64Regs, i64, i64imm>;
defm UDIVX : F3_12<"udivx", 0b001101, udiv, I64Regs, i64, i64imm>;
} // hasSideEffects = 1

} // Predicates = [Is64Bit]


Expand Down
69 changes: 67 additions & 2 deletions llvm/lib/Target/Sparc/SparcInstrAliases.td
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Expand Up @@ -286,11 +286,11 @@ multiclass cp_cond_alias<string cond, int condVal> {

// cb<cond> $imm
def : InstAlias<!strconcat(!strconcat("cb", cond), " $imm"),
(CBCOND brtarget:$imm, condVal), 0>;
(CPBCOND brtarget:$imm, condVal), 0>;

// cb<cond>,a $imm
def : InstAlias<!strconcat(!strconcat("cb", cond), ",a $imm"),
(CBCONDA brtarget:$imm, condVal), 0>;
(CPBCONDA brtarget:$imm, condVal), 0>;
}

// Instruction aliases for register conditional branches and moves.
Expand Down Expand Up @@ -331,6 +331,25 @@ multiclass reg_cond_alias<string rcond, int condVal> {
Requires<[Is64Bit]>;
}

// Instruction aliases for compare-and-branch.
multiclass cwb_cond_alias<string cond, int condVal> {
def : InstAlias<!strconcat(!strconcat("cwb", cond), " $rs1, $rs2, $imm"),
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Suggested change
def : InstAlias<!strconcat(!strconcat("cwb", cond), " $rs1, $rs2, $imm"),
def : InstAlias<"cwb" # cond # " $rs1, $rs2, $imm",

(CWBCONDrr cbtarget:$imm, condVal, IntRegs:$rs1, IntRegs:$rs2)>,
Requires<[HasOSA2011]>;
def : InstAlias<!strconcat(!strconcat("cwb", cond), " $rs1, $simm5, $imm"),
(CWBCONDri cbtarget:$imm, condVal, IntRegs:$rs1, simm5Op:$simm5)>,
Requires<[HasOSA2011]>;
}

multiclass cxb_cond_alias<string cond, int condVal> {
def : InstAlias<!strconcat(!strconcat("cxb", cond), " $rs1, $rs2, $imm"),
(CXBCONDrr cbtarget:$imm, condVal, IntRegs:$rs1, IntRegs:$rs2)>,
Requires<[HasOSA2011]>;
def : InstAlias<!strconcat(!strconcat("cxb", cond), " $rs1, $simm5, $imm"),
(CXBCONDri cbtarget:$imm, condVal, IntRegs:$rs1, simm5Op:$simm5)>,
Requires<[HasOSA2011]>;
}

defm : int_cond_alias<"a", 0b1000>;
defm : int_cond_alias<"n", 0b0000>;
defm : int_cond_alias<"ne", 0b1001>;
Expand Down Expand Up @@ -408,6 +427,46 @@ defm : reg_cond_alias<"ne", 0b101>;
defm : reg_cond_alias<"gz", 0b110>;
defm : reg_cond_alias<"gez", 0b111>;

defm : cwb_cond_alias<"ne", 0b1001>;
defm : cwb_cond_alias<"e", 0b0001>;
defm : cwb_cond_alias<"g", 0b1010>;
defm : cwb_cond_alias<"le", 0b0010>;
defm : cwb_cond_alias<"ge", 0b1011>;
defm : cwb_cond_alias<"l", 0b0011>;
defm : cwb_cond_alias<"gu", 0b1100>;
defm : cwb_cond_alias<"leu", 0b0100>;
defm : cwb_cond_alias<"cc", 0b1101>;
defm : cwb_cond_alias<"cs", 0b0101>;
defm : cwb_cond_alias<"pos", 0b1110>;
defm : cwb_cond_alias<"neg", 0b0110>;
defm : cwb_cond_alias<"vc", 0b1111>;
defm : cwb_cond_alias<"vs", 0b0111>;
let EmitPriority = 0 in
{
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Suggested change
let EmitPriority = 0 in
{
let EmitPriority = 0 in {

defm : cwb_cond_alias<"geu", 0b1101>; // same as cc
defm : cwb_cond_alias<"lu", 0b0101>; // same as cs
}

defm : cxb_cond_alias<"ne", 0b1001>;
defm : cxb_cond_alias<"e", 0b0001>;
defm : cxb_cond_alias<"g", 0b1010>;
defm : cxb_cond_alias<"le", 0b0010>;
defm : cxb_cond_alias<"ge", 0b1011>;
defm : cxb_cond_alias<"l", 0b0011>;
defm : cxb_cond_alias<"gu", 0b1100>;
defm : cxb_cond_alias<"leu", 0b0100>;
defm : cxb_cond_alias<"cc", 0b1101>;
defm : cxb_cond_alias<"cs", 0b0101>;
defm : cxb_cond_alias<"pos", 0b1110>;
defm : cxb_cond_alias<"neg", 0b0110>;
defm : cxb_cond_alias<"vc", 0b1111>;
defm : cxb_cond_alias<"vs", 0b0111>;
let EmitPriority = 0 in
{
defm : cxb_cond_alias<"geu", 0b1101>; // same as cc
defm : cxb_cond_alias<"lu", 0b0101>; // same as cs
}

// Section A.3 Synthetic Instructions

// Most are marked as Emit=0, so that they are not used for disassembly. This is
Expand Down Expand Up @@ -665,3 +724,9 @@ def : InstAlias<"signx $rs1, $rd", (SRArr IntRegs:$rd, IntRegs:$rs1, G0), 0>, Re

// sir -> sir 0
def : InstAlias<"sir", (SIR 0), 0>;

// pause reg_or_imm -> wrasr %g0, reg_or_imm, %asr27
let Predicates = [HasOSA2011] in {
def : InstAlias<"pause $rs2", (WRASRrr ASR27, G0, IntRegs:$rs2), 1>;
def : InstAlias<"pause $simm13", (WRASRri ASR27, G0, simm13Op:$simm13), 1>;
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Indentation

Suggested change
def : InstAlias<"pause $rs2", (WRASRrr ASR27, G0, IntRegs:$rs2), 1>;
def : InstAlias<"pause $simm13", (WRASRri ASR27, G0, simm13Op:$simm13), 1>;
def : InstAlias<"pause $rs2", (WRASRrr ASR27, G0, IntRegs:$rs2)>;
def : InstAlias<"pause $simm13", (WRASRri ASR27, G0, simm13Op:$simm13)>;

} // Predicates = [HasOSA2011]
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