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[LLVM][CodeGen][SVE] Add ISel for bfloat scalable vector compares. #138707

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Merged
merged 1 commit into from
May 8, 2025
Merged

[LLVM][CodeGen][SVE] Add ISel for bfloat scalable vector compares. #138707

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6 changes: 3 additions & 3 deletions llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -1758,18 +1758,18 @@ AArch64TargetLowering::AArch64TargetLowering(const TargetMachine &TM,

for (auto Opcode :
{ISD::FCEIL, ISD::FDIV, ISD::FFLOOR, ISD::FNEARBYINT, ISD::FRINT,
ISD::FROUND, ISD::FROUNDEVEN, ISD::FSQRT, ISD::FTRUNC}) {
ISD::FROUND, ISD::FROUNDEVEN, ISD::FSQRT, ISD::FTRUNC, ISD::SETCC}) {
setOperationPromotedToType(Opcode, MVT::nxv2bf16, MVT::nxv2f32);
setOperationPromotedToType(Opcode, MVT::nxv4bf16, MVT::nxv4f32);
setOperationAction(Opcode, MVT::nxv8bf16, Expand);
setOperationPromotedToType(Opcode, MVT::nxv8bf16, MVT::nxv8f32);
}

if (!Subtarget->hasSVEB16B16()) {
for (auto Opcode : {ISD::FADD, ISD::FMA, ISD::FMAXIMUM, ISD::FMAXNUM,
ISD::FMINIMUM, ISD::FMINNUM, ISD::FMUL, ISD::FSUB}) {
setOperationPromotedToType(Opcode, MVT::nxv2bf16, MVT::nxv2f32);
setOperationPromotedToType(Opcode, MVT::nxv4bf16, MVT::nxv4f32);
setOperationAction(Opcode, MVT::nxv8bf16, Expand);
setOperationPromotedToType(Opcode, MVT::nxv8bf16, MVT::nxv8f32);
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@paulwalker-arm paulwalker-arm May 6, 2025

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Strictly speaking this is not required, but given it's related to legalisation of nxv8bf16 as above I figured it was worth keeping the two lines consistent?

}
}

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