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[AMDGPU] Fix regclass check for PackedF32InputMods in AsmParser. #138767

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Merged
merged 1 commit into from
May 7, 2025
Merged

[AMDGPU] Fix regclass check for PackedF32InputMods in AsmParser. #138767

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4 changes: 2 additions & 2 deletions llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -337,8 +337,8 @@ class AMDGPUOperand : public MCParsedAsmOperand {
return isRegOrImmWithInputMods(AMDGPU::VS_32RegClassID, MVT::v2f16);
}

bool isPackedFP32InputMods() const {
return isRegOrImmWithInputMods(AMDGPU::VS_64RegClassID, MVT::v2f32);
bool isPackedVGPRFP32InputMods() const {
return isRegOrImmWithInputMods(AMDGPU::VReg_64RegClassID, MVT::v2f32);
}

bool isVReg() const {
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8 changes: 6 additions & 2 deletions llvm/lib/Target/AMDGPU/SIInstrInfo.td
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Expand Up @@ -1550,6 +1550,10 @@ class PackedFPInputModsMatchClass <int opSize> : AsmOperandClass {
let PredicateMethod = "isPackedFP"#opSize#"InputMods";
}

class PackedVGPRFPInputModsMatchClass <int opSize> : PackedFPInputModsMatchClass<opSize> {
let PredicateMethod = "isPackedVGPRFP"#opSize#"InputMods";
}

class PackedIntInputModsMatchClass <int opSize> : AsmOperandClass {
let Name = "PackedInt"#opSize#"InputMods";
let ParserMethod = "parseRegOrImm";
Expand All @@ -1559,7 +1563,7 @@ class PackedIntInputModsMatchClass <int opSize> : AsmOperandClass {

def PackedF16InputModsMatchClass : PackedFPInputModsMatchClass<16>;
def PackedI16InputModsMatchClass : PackedIntInputModsMatchClass<16>;
def PackedF32InputModsMatchClass : PackedFPInputModsMatchClass<32>;
def PackedVGPRF32InputModsMatchClass : PackedVGPRFPInputModsMatchClass<32>;

class PackedFPInputMods <PackedFPInputModsMatchClass matchClass> : InputMods <matchClass> {
let PrintMethod = "printOperandAndFPInputMods";
Expand All @@ -1571,7 +1575,7 @@ class PackedIntInputMods <PackedIntInputModsMatchClass matchClass> : InputMods <

def PackedF16InputMods : PackedFPInputMods<PackedF16InputModsMatchClass>;
def PackedI16InputMods : PackedIntInputMods<PackedI16InputModsMatchClass>;
def PackedF32InputMods : PackedFPInputMods<PackedF32InputModsMatchClass>;
def PackedVGPRF32InputMods : PackedFPInputMods<PackedVGPRF32InputModsMatchClass>;

def MFMALdScaleModifierOp : TImmLeaf<i32, [{
return isUInt<2>(Imm);
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2 changes: 1 addition & 1 deletion llvm/lib/Target/AMDGPU/VOP3Instructions.td
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Expand Up @@ -1049,7 +1049,7 @@ class VOP3_CVT_SCALE_SR_PK_F4_F32_TiedInput_Profile<VOPProfile P>

let Src0RC64 = !if(!gt(P.Src0VT.Size, 32), getVOP3VRegSrcForVT<P.Src0VT>.ret,
getVOP3SrcForVT<P.Src0VT>.ret);
let InsVOP3OpSel = (ins PackedF32InputMods: $src0_modifiers, Src0RC64:$src0,
let InsVOP3OpSel = (ins PackedVGPRF32InputMods: $src0_modifiers, Src0RC64:$src0,
Int32InputMods: $src1_modifiers, Src1RC64:$src1,
FP32InputMods: $src2_modifiers, Src2RC64:$src2,
VGPR_32:$vdst_in, op_sel0:$op_sel);
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2 changes: 1 addition & 1 deletion llvm/test/MC/AMDGPU/gfx950_err.s
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Expand Up @@ -495,5 +495,5 @@ v_cvt_scalef32_2xpk16_bf6_f32 v[0:5], s[0:15], v[6:21], v16
// GFX950: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction
v_cvt_scalef32_2xpk16_bf6_f32 v[0:5], v[6:21], s[0:15], v16

// GFX950: v_cvt_scalef32_sr_pk_fp4_f32 v0, s[2:3]/*Invalid register, operand has 'VReg_64' register class*/, v4, v5
// GFX950: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction
v_cvt_scalef32_sr_pk_fp4_f32 v0, s[2:3], v4, v5