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[SelectionDAG] Rename MemSDNode::getOriginalAlign to getBaseAlign. NFC #139930

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Merged
topperc merged 1 commit into from
May 16, 2025
Merged

[SelectionDAG] Rename MemSDNode::getOriginalAlign to getBaseAlign. NFC #139930

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2 changes: 1 addition & 1 deletion llvm/include/llvm/CodeGen/SelectionDAGNodes.h
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Original file line number Diff line number Diff line change
Expand Up @@ -1386,7 +1386,7 @@ class MemSDNode : public SDNode {
bool writeMem() const { return MMO->isStore(); }

/// Returns alignment and volatility of the memory access
Align getOriginalAlign() const { return MMO->getBaseAlign(); }
Align getBaseAlign() const { return MMO->getBaseAlign(); }
Align getAlign() const { return MMO->getAlign(); }

/// Return the SubclassData value, without HasDebugValue. This contains an
Expand Down
39 changes: 19 additions & 20 deletions llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -12377,8 +12377,8 @@ SDValue DAGCombiner::visitMSTORE(SDNode *N) {
!MST->isCompressingStore() && !MST->isTruncatingStore())
return DAG.getStore(MST->getChain(), SDLoc(N), MST->getValue(),
MST->getBasePtr(), MST->getPointerInfo(),
MST->getOriginalAlign(),
MST->getMemOperand()->getFlags(), MST->getAAInfo());
MST->getBaseAlign(), MST->getMemOperand()->getFlags(),
MST->getAAInfo());

// Try transforming N to an indexed store.
if (CombineToPreIndexedLoadStore(N) || CombineToPostIndexedLoadStore(N))
Expand Down Expand Up @@ -12562,7 +12562,7 @@ SDValue DAGCombiner::visitMLOAD(SDNode *N) {
!MLD->isExpandingLoad() && MLD->getExtensionType() == ISD::NON_EXTLOAD) {
SDValue NewLd = DAG.getLoad(
N->getValueType(0), SDLoc(N), MLD->getChain(), MLD->getBasePtr(),
MLD->getPointerInfo(), MLD->getOriginalAlign(),
MLD->getPointerInfo(), MLD->getBaseAlign(),
MLD->getMemOperand()->getFlags(), MLD->getAAInfo(), MLD->getRanges());
return CombineTo(N, NewLd, NewLd.getValue(1));
}
Expand Down Expand Up @@ -13602,7 +13602,7 @@ SDValue DAGCombiner::CombineExtLoad(SDNode *N) {
SDValue SplitLoad =
DAG.getExtLoad(ExtType, SDLoc(LN0), SplitDstVT, LN0->getChain(),
BasePtr, LN0->getPointerInfo().getWithOffset(Offset),
SplitSrcVT, LN0->getOriginalAlign(),
SplitSrcVT, LN0->getBaseAlign(),
LN0->getMemOperand()->getFlags(), LN0->getAAInfo());

BasePtr = DAG.getMemBasePlusOffset(BasePtr, TypeSize::getFixed(Stride), DL);
Expand Down Expand Up @@ -15159,15 +15159,15 @@ SDValue DAGCombiner::reduceLoadWidth(SDNode *N) {
} else if (CR.getBitWidth() == BitSize)
NewRanges = OldRanges;
}
Load = DAG.getLoad(
VT, DL, LN0->getChain(), NewPtr,
LN0->getPointerInfo().getWithOffset(PtrOff), LN0->getOriginalAlign(),
LN0->getMemOperand()->getFlags(), LN0->getAAInfo(), NewRanges);
Load = DAG.getLoad(VT, DL, LN0->getChain(), NewPtr,
LN0->getPointerInfo().getWithOffset(PtrOff),
LN0->getBaseAlign(), LN0->getMemOperand()->getFlags(),
LN0->getAAInfo(), NewRanges);
} else
Load = DAG.getExtLoad(ExtType, DL, VT, LN0->getChain(), NewPtr,
LN0->getPointerInfo().getWithOffset(PtrOff), ExtVT,
LN0->getOriginalAlign(),
LN0->getMemOperand()->getFlags(), LN0->getAAInfo());
LN0->getBaseAlign(), LN0->getMemOperand()->getFlags(),
LN0->getAAInfo());

// Replace the old load's chain with the new load's chain.
WorklistRemover DeadNodes(*this);
Expand Down Expand Up @@ -20583,16 +20583,15 @@ ShrinkLoadReplaceStoreWithStore(const std::pair<unsigned, unsigned> &MaskInfo,
++OpsNarrowed;
if (UseTruncStore)
return DAG.getTruncStore(St->getChain(), SDLoc(St), IVal, Ptr,
St->getPointerInfo().getWithOffset(StOffset),
VT, St->getOriginalAlign());
St->getPointerInfo().getWithOffset(StOffset), VT,
St->getBaseAlign());

// Truncate down to the new size.
IVal = DAG.getNode(ISD::TRUNCATE, SDLoc(IVal), VT, IVal);

return DAG
.getStore(St->getChain(), SDLoc(St), IVal, Ptr,
St->getPointerInfo().getWithOffset(StOffset),
St->getOriginalAlign());
return DAG.getStore(St->getChain(), SDLoc(St), IVal, Ptr,
St->getPointerInfo().getWithOffset(StOffset),
St->getBaseAlign());
}

/// Look for sequence of load / op / store where op is one of 'or', 'xor', and
Expand Down Expand Up @@ -22113,11 +22112,11 @@ SDValue DAGCombiner::replaceStoreOfFPConstant(StoreSDNode *ST) {
AAMDNodes AAInfo = ST->getAAInfo();

SDValue St0 = DAG.getStore(Chain, DL, Lo, Ptr, ST->getPointerInfo(),
ST->getOriginalAlign(), MMOFlags, AAInfo);
ST->getBaseAlign(), MMOFlags, AAInfo);
Ptr = DAG.getMemBasePlusOffset(Ptr, TypeSize::getFixed(4), DL);
SDValue St1 = DAG.getStore(Chain, DL, Hi, Ptr,
ST->getPointerInfo().getWithOffset(4),
ST->getOriginalAlign(), MMOFlags, AAInfo);
ST->getBaseAlign(), MMOFlags, AAInfo);
return DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
St0, St1);
}
Expand Down Expand Up @@ -22588,13 +22587,13 @@ SDValue DAGCombiner::splitMergedValStore(StoreSDNode *ST) {
SDValue Ptr = ST->getBasePtr();
// Lower value store.
SDValue St0 = DAG.getStore(Chain, DL, Lo, Ptr, ST->getPointerInfo(),
ST->getOriginalAlign(), MMOFlags, AAInfo);
ST->getBaseAlign(), MMOFlags, AAInfo);
Ptr =
DAG.getMemBasePlusOffset(Ptr, TypeSize::getFixed(HalfValBitSize / 8), DL);
// Higher value store.
SDValue St1 = DAG.getStore(
St0, DL, Hi, Ptr, ST->getPointerInfo().getWithOffset(HalfValBitSize / 8),
ST->getOriginalAlign(), MMOFlags, AAInfo);
ST->getBaseAlign(), MMOFlags, AAInfo);
return St1;
}

Expand Down
37 changes: 18 additions & 19 deletions llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -441,7 +441,7 @@ SDValue SelectionDAGLegalize::OptimizeFloatStore(StoreSDNode* ST) {
bitcastToAPInt().zextOrTrunc(32),
SDLoc(CFP), MVT::i32);
return DAG.getStore(Chain, dl, Con, Ptr, ST->getPointerInfo(),
ST->getOriginalAlign(), MMOFlags, AAInfo);
ST->getBaseAlign(), MMOFlags, AAInfo);
}

if (CFP->getValueType(0) == MVT::f64 &&
Expand All @@ -451,7 +451,7 @@ SDValue SelectionDAGLegalize::OptimizeFloatStore(StoreSDNode* ST) {
SDValue Con = DAG.getConstant(CFP->getValueAPF().bitcastToAPInt().
zextOrTrunc(64), SDLoc(CFP), MVT::i64);
return DAG.getStore(Chain, dl, Con, Ptr, ST->getPointerInfo(),
ST->getOriginalAlign(), MMOFlags, AAInfo);
ST->getBaseAlign(), MMOFlags, AAInfo);
}

if (TLI.isTypeLegal(MVT::i32) && !ST->isVolatile()) {
Expand All @@ -465,11 +465,11 @@ SDValue SelectionDAGLegalize::OptimizeFloatStore(StoreSDNode* ST) {
std::swap(Lo, Hi);

Lo = DAG.getStore(Chain, dl, Lo, Ptr, ST->getPointerInfo(),
ST->getOriginalAlign(), MMOFlags, AAInfo);
ST->getBaseAlign(), MMOFlags, AAInfo);
Ptr = DAG.getMemBasePlusOffset(Ptr, TypeSize::getFixed(4), dl);
Hi = DAG.getStore(Chain, dl, Hi, Ptr,
ST->getPointerInfo().getWithOffset(4),
ST->getOriginalAlign(), MMOFlags, AAInfo);
ST->getBaseAlign(), MMOFlags, AAInfo);

return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo, Hi);
}
Expand Down Expand Up @@ -525,7 +525,7 @@ void SelectionDAGLegalize::LegalizeStoreOps(SDNode *Node) {
"Can only promote stores to same size type");
Value = DAG.getNode(ISD::BITCAST, dl, NVT, Value);
SDValue Result = DAG.getStore(Chain, dl, Value, Ptr, ST->getPointerInfo(),
ST->getOriginalAlign(), MMOFlags, AAInfo);
ST->getBaseAlign(), MMOFlags, AAInfo);
ReplaceNode(SDValue(Node, 0), Result);
break;
}
Expand All @@ -548,7 +548,7 @@ void SelectionDAGLegalize::LegalizeStoreOps(SDNode *Node) {
Value = DAG.getZeroExtendInReg(Value, dl, StVT);
SDValue Result =
DAG.getTruncStore(Chain, dl, Value, Ptr, ST->getPointerInfo(), NVT,
ST->getOriginalAlign(), MMOFlags, AAInfo);
ST->getBaseAlign(), MMOFlags, AAInfo);
ReplaceNode(SDValue(Node, 0), Result);
} else if (!StVT.isVector() && !isPowerOf2_64(StWidth.getFixedValue())) {
// If not storing a power-of-2 number of bits, expand as two stores.
Expand All @@ -571,7 +571,7 @@ void SelectionDAGLegalize::LegalizeStoreOps(SDNode *Node) {
// TRUNCSTORE:i24 X -> TRUNCSTORE:i16 X, TRUNCSTORE@+2:i8 (srl X, 16)
// Store the bottom RoundWidth bits.
Lo = DAG.getTruncStore(Chain, dl, Value, Ptr, ST->getPointerInfo(),
RoundVT, ST->getOriginalAlign(), MMOFlags, AAInfo);
RoundVT, ST->getBaseAlign(), MMOFlags, AAInfo);

// Store the remaining ExtraWidth bits.
IncrementSize = RoundWidth / 8;
Expand All @@ -583,7 +583,7 @@ void SelectionDAGLegalize::LegalizeStoreOps(SDNode *Node) {
TLI.getShiftAmountTy(Value.getValueType(), DL)));
Hi = DAG.getTruncStore(Chain, dl, Hi, Ptr,
ST->getPointerInfo().getWithOffset(IncrementSize),
ExtraVT, ST->getOriginalAlign(), MMOFlags, AAInfo);
ExtraVT, ST->getBaseAlign(), MMOFlags, AAInfo);
} else {
// Big endian - avoid unaligned stores.
// TRUNCSTORE:i24 X -> TRUNCSTORE:i16 (srl X, 8), TRUNCSTORE@+2:i8 X
Expand All @@ -593,7 +593,7 @@ void SelectionDAGLegalize::LegalizeStoreOps(SDNode *Node) {
DAG.getConstant(ExtraWidth, dl,
TLI.getShiftAmountTy(Value.getValueType(), DL)));
Hi = DAG.getTruncStore(Chain, dl, Hi, Ptr, ST->getPointerInfo(), RoundVT,
ST->getOriginalAlign(), MMOFlags, AAInfo);
ST->getBaseAlign(), MMOFlags, AAInfo);

// Store the remaining ExtraWidth bits.
IncrementSize = RoundWidth / 8;
Expand All @@ -602,7 +602,7 @@ void SelectionDAGLegalize::LegalizeStoreOps(SDNode *Node) {
Ptr.getValueType()));
Lo = DAG.getTruncStore(Chain, dl, Value, Ptr,
ST->getPointerInfo().getWithOffset(IncrementSize),
ExtraVT, ST->getOriginalAlign(), MMOFlags, AAInfo);
ExtraVT, ST->getBaseAlign(), MMOFlags, AAInfo);
}

// The order of the stores doesn't matter.
Expand Down Expand Up @@ -638,16 +638,15 @@ void SelectionDAGLegalize::LegalizeStoreOps(SDNode *Node) {
if (TLI.isTypeLegal(StVT)) {
Value = DAG.getNode(ISD::TRUNCATE, dl, StVT, Value);
Result = DAG.getStore(Chain, dl, Value, Ptr, ST->getPointerInfo(),
ST->getOriginalAlign(), MMOFlags, AAInfo);
ST->getBaseAlign(), MMOFlags, AAInfo);
} else {
// The in-memory type isn't legal. Truncate to the type it would promote
// to, and then do a truncstore.
Value = DAG.getNode(ISD::TRUNCATE, dl,
TLI.getTypeToTransformTo(*DAG.getContext(), StVT),
Value);
Result =
DAG.getTruncStore(Chain, dl, Value, Ptr, ST->getPointerInfo(), StVT,
ST->getOriginalAlign(), MMOFlags, AAInfo);
Result = DAG.getTruncStore(Chain, dl, Value, Ptr, ST->getPointerInfo(),
StVT, ST->getBaseAlign(), MMOFlags, AAInfo);
}

ReplaceNode(SDValue(Node, 0), Result);
Expand Down Expand Up @@ -753,7 +752,7 @@ void SelectionDAGLegalize::LegalizeLoadOps(SDNode *Node) {

SDValue Result = DAG.getExtLoad(NewExtType, dl, Node->getValueType(0),
Chain, Ptr, LD->getPointerInfo(), NVT,
LD->getOriginalAlign(), MMOFlags, AAInfo);
LD->getBaseAlign(), MMOFlags, AAInfo);

Ch = Result.getValue(1); // The chain.

Expand Down Expand Up @@ -792,7 +791,7 @@ void SelectionDAGLegalize::LegalizeLoadOps(SDNode *Node) {
// EXTLOAD:i24 -> ZEXTLOAD:i16 | (shl EXTLOAD@+2:i8, 16)
// Load the bottom RoundWidth bits.
Lo = DAG.getExtLoad(ISD::ZEXTLOAD, dl, Node->getValueType(0), Chain, Ptr,
LD->getPointerInfo(), RoundVT, LD->getOriginalAlign(),
LD->getPointerInfo(), RoundVT, LD->getBaseAlign(),
MMOFlags, AAInfo);

// Load the remaining ExtraWidth bits.
Expand All @@ -801,7 +800,7 @@ void SelectionDAGLegalize::LegalizeLoadOps(SDNode *Node) {
DAG.getMemBasePlusOffset(Ptr, TypeSize::getFixed(IncrementSize), dl);
Hi = DAG.getExtLoad(ExtType, dl, Node->getValueType(0), Chain, Ptr,
LD->getPointerInfo().getWithOffset(IncrementSize),
ExtraVT, LD->getOriginalAlign(), MMOFlags, AAInfo);
ExtraVT, LD->getBaseAlign(), MMOFlags, AAInfo);

// Build a factor node to remember that this load is independent of
// the other one.
Expand All @@ -821,7 +820,7 @@ void SelectionDAGLegalize::LegalizeLoadOps(SDNode *Node) {
// EXTLOAD:i24 -> (shl EXTLOAD:i16, 8) | ZEXTLOAD@+2:i8
// Load the top RoundWidth bits.
Hi = DAG.getExtLoad(ExtType, dl, Node->getValueType(0), Chain, Ptr,
LD->getPointerInfo(), RoundVT, LD->getOriginalAlign(),
LD->getPointerInfo(), RoundVT, LD->getBaseAlign(),
MMOFlags, AAInfo);

// Load the remaining ExtraWidth bits.
Expand All @@ -830,7 +829,7 @@ void SelectionDAGLegalize::LegalizeLoadOps(SDNode *Node) {
DAG.getMemBasePlusOffset(Ptr, TypeSize::getFixed(IncrementSize), dl);
Lo = DAG.getExtLoad(ISD::ZEXTLOAD, dl, Node->getValueType(0), Chain, Ptr,
LD->getPointerInfo().getWithOffset(IncrementSize),
ExtraVT, LD->getOriginalAlign(), MMOFlags, AAInfo);
ExtraVT, LD->getBaseAlign(), MMOFlags, AAInfo);

// Build a factor node to remember that this load is independent of
// the other one.
Expand Down
12 changes: 6 additions & 6 deletions llvm/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp
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Expand Up @@ -967,8 +967,8 @@ SDValue DAGTypeLegalizer::SoftenFloatRes_LOAD(SDNode *N) {
if (L->getExtensionType() == ISD::NON_EXTLOAD) {
NewL = DAG.getLoad(L->getAddressingMode(), L->getExtensionType(), NVT, dl,
L->getChain(), L->getBasePtr(), L->getOffset(),
L->getPointerInfo(), NVT, L->getOriginalAlign(),
MMOFlags, L->getAAInfo());
L->getPointerInfo(), NVT, L->getBaseAlign(), MMOFlags,
L->getAAInfo());
// Legalized the chain result - switch anything that used the old chain to
// use the new one.
ReplaceValueWith(SDValue(N, 1), NewL.getValue(1));
Expand All @@ -978,8 +978,8 @@ SDValue DAGTypeLegalizer::SoftenFloatRes_LOAD(SDNode *N) {
// Do a non-extending load followed by FP_EXTEND.
NewL = DAG.getLoad(L->getAddressingMode(), ISD::NON_EXTLOAD, L->getMemoryVT(),
dl, L->getChain(), L->getBasePtr(), L->getOffset(),
L->getPointerInfo(), L->getMemoryVT(),
L->getOriginalAlign(), MMOFlags, L->getAAInfo());
L->getPointerInfo(), L->getMemoryVT(), L->getBaseAlign(),
MMOFlags, L->getAAInfo());
// Legalized the chain result - switch anything that used the old chain to
// use the new one.
ReplaceValueWith(SDValue(N, 1), NewL.getValue(1));
Expand Down Expand Up @@ -3105,7 +3105,7 @@ SDValue DAGTypeLegalizer::PromoteFloatRes_LOAD(SDNode *N) {
SDValue newL = DAG.getLoad(
L->getAddressingMode(), L->getExtensionType(), IVT, SDLoc(N),
L->getChain(), L->getBasePtr(), L->getOffset(), L->getPointerInfo(), IVT,
L->getOriginalAlign(), L->getMemOperand()->getFlags(), L->getAAInfo());
L->getBaseAlign(), L->getMemOperand()->getFlags(), L->getAAInfo());
// Legalize the chain result by replacing uses of the old value chain with the
// new one
ReplaceValueWith(SDValue(N, 1), newL.getValue(1));
Expand Down Expand Up @@ -3531,7 +3531,7 @@ SDValue DAGTypeLegalizer::SoftPromoteHalfRes_LOAD(SDNode *N) {
SDValue NewL =
DAG.getLoad(L->getAddressingMode(), L->getExtensionType(), MVT::i16,
SDLoc(N), L->getChain(), L->getBasePtr(), L->getOffset(),
L->getPointerInfo(), MVT::i16, L->getOriginalAlign(),
L->getPointerInfo(), MVT::i16, L->getBaseAlign(),
L->getMemOperand()->getFlags(), L->getAAInfo());
// Legalize the chain result by replacing uses of the old value chain with the
// new one
Expand Down
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