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25 changes: 19 additions & 6 deletions llvm/lib/Target/RISCV/RISCVSchedule.td
Original file line number Diff line number Diff line change
Expand Up @@ -454,18 +454,31 @@ def : ReadAdvance<ReadFRoundF128, 0>;
}
}

multiclass UnsupportedSchedZfa : UnsupportedSchedZfaWithQ {
multiclass UnsupportedSchedZfaWithD : UnsupportedSchedZfaWithQ {
let Unsupported = true in {
def : WriteRes<WriteFRoundF16, []>;
def : WriteRes<WriteFRoundF32, []>;
def : WriteRes<WriteFRoundF64, []>;
def : WriteRes<WriteFLI16, []>;
def : WriteRes<WriteFLI32, []>;
def : WriteRes<WriteFLI64, []>;

def : ReadAdvance<ReadFRoundF32, 0>;
def : ReadAdvance<ReadFRoundF64, 0>;
}
}

multiclass UnsupportedSchedZfaWithZfh {
let Unsupported = true in {
def : WriteRes<WriteFRoundF16, []>;
def : WriteRes<WriteFLI16, []>;

def : ReadAdvance<ReadFRoundF16, 0>;
}
}

multiclass UnsupportedSchedZfa : UnsupportedSchedZfaWithD,
UnsupportedSchedZfaWithZfh {
let Unsupported = true in {
def : WriteRes<WriteFRoundF32, []>;
def : WriteRes<WriteFLI32, []>;

def : ReadAdvance<ReadFRoundF32, 0>;
} // Unsupported = true
}

Expand Down