Skip to content

[AArch64][SDAG] Fix selection of extend of v1if16 SETCC #140274

New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Merged
MacDue merged 2 commits into from
Jun 6, 2025
Merged

[AArch64][SDAG] Fix selection of extend of v1if16 SETCC #140274

Show file tree
Hide file tree
Changes from all commits
Commits
Show all changes
2 commits
Select commit Hold shift + click to select a range
1df4700
[AArch64] Fix selection of extend of v1if16 SETCC
MacDue May 16, 2025
dc4bf0c
Use poison
MacDue May 21, 2025
File filter

Filter by extension

Filter by extension
Conversations
Failed to load comments.
Loading
Jump to
Jump to file
Failed to load files.
Loading
Diff view
Diff view
8 changes: 6 additions & 2 deletions llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -6623,8 +6623,12 @@ SDValue DAGTypeLegalizer::WidenVecRes_SETCC(SDNode *N) {
InOp1 = GetWidenedVector(InOp1);
InOp2 = GetWidenedVector(InOp2);
} else {
InOp1 = DAG.WidenVector(InOp1, SDLoc(N));
InOp2 = DAG.WidenVector(InOp2, SDLoc(N));
SDValue Poison = DAG.getPOISON(WidenInVT);
SDValue ZeroIdx = DAG.getVectorIdxConstant(0, SDLoc(N));
InOp1 = DAG.getNode(ISD::INSERT_SUBVECTOR, SDLoc(N), WidenInVT, Poison,
InOp1, ZeroIdx);
InOp2 = DAG.getNode(ISD::INSERT_SUBVECTOR, SDLoc(N), WidenInVT, Poison,
InOp2, ZeroIdx);
}

// Assume that the input and output will be widen appropriately. If not,
Expand Down
16 changes: 16 additions & 0 deletions llvm/test/CodeGen/AArch64/arm64-neon-v1i1-setcc.ll
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -249,3 +249,19 @@ if.then:
if.end:
ret i32 1;
}

define <1 x i64> @test_zext_half(<1 x half> %v1) {
; CHECK-LABEL: test_zext_half:
; CHECK: // %bb.0:
; CHECK-NEXT: // kill: def $h0 killed $h0 def $d0
; CHECK-NEXT: mov w8, #1 // =0x1
; CHECK-NEXT: fcvtl v0.4s, v0.4h
; CHECK-NEXT: fmov d1, x8
; CHECK-NEXT: fcmgt v0.4s, v0.4s, #0.0
; CHECK-NEXT: xtn v0.4h, v0.4s
; CHECK-NEXT: and v0.8b, v0.8b, v1.8b
; CHECK-NEXT: ret
%1 = fcmp ogt <1 x half> %v1, zeroinitializer
%2 = zext <1 x i1> %1 to <1 x i64>
ret <1 x i64> %2
}