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[CIR] Upstream support for lowering cir.switch to LLVM #140425
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| Original file line number | Diff line number | Diff line change | ||||
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@@ -1038,6 +1038,37 @@ mlir::LogicalResult CIRToLLVMGlobalOpLowering::matchAndRewrite( | |||||
| return mlir::success(); | ||||||
| } | ||||||
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| mlir::LogicalResult CIRToLLVMSwitchFlatOpLowering::matchAndRewrite( | ||||||
| cir::SwitchFlatOp op, OpAdaptor adaptor, | ||||||
| mlir::ConversionPatternRewriter &rewriter) const { | ||||||
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| llvm::SmallVector<mlir::APInt, 8> caseValues; | ||||||
| if (op.getCaseValues()) { | ||||||
| for (mlir::Attribute val : op.getCaseValues()) { | ||||||
| auto intAttr = dyn_cast<cir::IntAttr>(val); | ||||||
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| auto intAttr = dyn_cast<cir::IntAttr>(val); | |
| auto intAttr = cast<cir::IntAttr>(val); |
Make this assert.
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Don't need braces for loops with single-line bodies.
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No braces
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Is this
ifnecessary? I think it there are no case values we just won't enter theforloop below.