[RISCV] Add LD_RV32/SD_RV32 to a few more functions in RISCVInstrInfo.

[topperc]

isLoadFromStackSlot/isStoreToStackSlot/getMemOperandsWithOffsetWidth

The first 2 probably requires spills/reloads which we don't use LD_RV32/SD_RV32 for yet.

I think getMemOperandsWithOffsetWidth is mainly used for load/store clustering. I think we can assume this just works, but I can try to add a test if reviewers want.

[llvmbot]

@llvm/pr-subscribers-backend-risc-v

Author: Craig Topper (topperc)

Changes

isLoadFromStackSlot/isStoreToStackSlot/getMemOperandsWithOffsetWidth

The first 2 probably requires spills/reloads which we don't use LD_RV32/SD_RV32 for yet.

I think getMemOperandsWithOffsetWidth is mainly used for load/store clustering. I think we can assume this just works, but I can try to add a test if reviewers want.

---

Full diff: https://github.com/llvm/llvm-project/pull/140640.diff

1 Files Affected:

• (modified) llvm/lib/Target/RISCV/RISCVInstrInfo.cpp (+4)

diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp b/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
index e9e5fa8d8042a..6c6ccc2c6244d 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
@@ -156,6 +156,7 @@ Register RISCVInstrInfo::isLoadFromStackSlot(const MachineInstr &MI,
     MemBytes = TypeSize::getFixed(4);
     break;
   case RISCV::LD:
+  case RISCV::LD_RV32:
   case RISCV::FLD:
     MemBytes = TypeSize::getFixed(8);
     break;
@@ -206,6 +207,7 @@ Register RISCVInstrInfo::isStoreToStackSlot(const MachineInstr &MI,
     MemBytes = TypeSize::getFixed(4);
     break;
   case RISCV::SD:
+  case RISCV::SD_RV32:
   case RISCV::FSD:
     MemBytes = TypeSize::getFixed(8);
     break;
@@ -3055,8 +3057,10 @@ bool RISCVInstrInfo::getMemOperandsWithOffsetWidth(
   case RISCV::SW_INX:
   case RISCV::FSW:
   case RISCV::LD:
+  case RISCV::LD_RV32:
   case RISCV::FLD:
   case RISCV::SD:
+  case RISCV::SD_RV32:
   case RISCV::FSD:
     break;
   default:

[preames]

LGTM

Mildly not a fan of adding code which isn't yet exercised, but a) the change is obvious, and b) I trust you to follow through on the spill/fill bits in a reasonable timeline.

[topperc]

LGTM

Mildly not a fan of adding code which isn't yet exercised, but a) the change is obvious, and b) I trust you to follow through on the spill/fill bits in a reasonable timeline.

The spill slots for Zdinx are only 4 byte aligned so I think we can only use them for spill for unaligned-scalar-mem.