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[AMDGPU][MISched] Allow memory ops of different base pointers to be clustered #140674

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[AMDGPU][MISched] Allow memory ops of different base pointers to be clustered #140674

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584a643
[AMDGPU][MISched] Allow memory ops of different base pointers to be c…
choikwa May 12, 2025
b453d6c
Fix lit test failures, remove no-cluster test since we now expect to …
choikwa May 20, 2025
608b002
NFC formatting
choikwa May 20, 2025
8dba56c
Addressed feedback: Change to Enable, Reject scalar and vector cluste…
choikwa May 21, 2025
952d5f7
Add flag test .ll file. Couldn't get a contrived .mir testcase to not…
choikwa May 22, 2025
a05a360
NFC formatting
choikwa May 22, 2025
0f00dab
use isVMEM & isSMRD
choikwa May 22, 2025
031db99
use != and isVMEM only
choikwa May 22, 2025
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15 changes: 4 additions & 11 deletions llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -590,17 +590,10 @@ bool SIInstrInfo::shouldClusterMemOps(ArrayRef<const MachineOperand *> BaseOps1,
if (!memOpsHaveSameAddrspace(FirstLdSt, BaseOps1, SecondLdSt, BaseOps2))
return false;

// Don't cluster scalar and vecter memory ops
const MachineFunction &MF = *FirstLdSt.getParent()->getParent();
const MachineRegisterInfo &MRI = MF.getRegInfo();
if (FirstLdSt.getOperand(0).isReg() && SecondLdSt.getOperand(0).isReg()) {
bool isFirstVecReg =
RI.isVectorRegister(MRI, FirstLdSt.getOperand(0).getReg());
bool isSecondVecReg =
RI.isVectorRegister(MRI, SecondLdSt.getOperand(0).getReg());
if (isFirstVecReg ^ isSecondVecReg)
return false;
}
// Don't cluster scalar and vector memory ops
if ((isVMEM(FirstLdSt) && isSMRD(SecondLdSt)) ||
(isSMRD(FirstLdSt) && isVMEM(SecondLdSt)))
return false;
} else {
// If the mem ops (to be clustered) do not have the same base ptr, then
// they should not be clustered
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