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[AMDGPU][True16][CodeGen] select vgpr16 for asm inline 16bit vreg #140946

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Merged
merged 2 commits into from
May 21, 2025
Merged

[AMDGPU][True16][CodeGen] select vgpr16 for asm inline 16bit vreg #140946

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c1b6d35
16bit for asm inline reg
broxigarchen May 21, 2025
67d4d9f
auto generate check line
broxigarchen May 21, 2025
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3 changes: 2 additions & 1 deletion llvm/lib/Target/AMDGPU/SIISelLowering.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -16062,7 +16062,8 @@ SITargetLowering::getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI_,
case 'v':
switch (BitWidth) {
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@jayfoad jayfoad May 22, 2025

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switch seems overkill here. Could just handle it with:

  if (BitWidth == 16 && !Subtarget->useRealTrue16Insts())
    BitWidth = 32;

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@jayfoad jayfoad May 22, 2025

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Or even move the handling for the BitWidth == 16 case inside getVGPRClassForBitWidth?

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@arsenm arsenm May 22, 2025

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This reminds me we need constraints for the aligned and unaligned versions of register classes

case 16:
RC = &AMDGPU::VGPR_32RegClass;
RC = Subtarget->useRealTrue16Insts() ? &AMDGPU::VGPR_16RegClass
: &AMDGPU::VGPR_32RegClass;
break;
default:
RC = TRI->getVGPRClassForBitWidth(BitWidth);
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48 changes: 48 additions & 0 deletions llvm/test/CodeGen/AMDGPU/inlineasm-16-fake16.ll
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@@ -0,0 +1,48 @@
; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=-real-true16 < %s | FileCheck -enable-var-scope -check-prefixes=GFX11 %s
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@shiltian shiltian May 21, 2025

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can you auto generate check lines?

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@broxigarchen broxigarchen May 21, 2025

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Sure


; GFX11-LABEL: {{^}}s_input_output_i16:
; GFX11: s_mov_b32 s[[REG:[0-9]+]], -1
; GFX11: ; use s[[REG]]
define amdgpu_kernel void @s_input_output_i16() #0 {
%v = tail call i16 asm sideeffect "s_mov_b32 $0, -1", "=s"()
tail call void asm sideeffect "; use $0", "s"(i16 %v) #0
ret void
}

; GFX11-LABEL: {{^}}s_input_output_f16:
; GFX11: s_mov_b32 s[[REG:[0-9]+]], -1
; GFX11: ; use s[[REG]]
define amdgpu_kernel void @s_input_output_f16() #0 {
%v = tail call half asm sideeffect "s_mov_b32 $0, -1", "=s"() #0
tail call void asm sideeffect "; use $0", "s"(half %v)
ret void
}

; GFX11-LABEL: {{^}}v_input_output_f16:
; GFX11: v_mov_b32 v[[REG:[0-9]+]], -1
; GFX11: ; use v[[REG]]
define amdgpu_kernel void @v_input_output_f16() #0 {
%v = tail call half asm sideeffect "v_mov_b32 $0, -1", "=v"() #0
tail call void asm sideeffect "; use $0", "v"(half %v)
ret void
}

; GFX11-LABEL: {{^}}v_input_output_i16:
; GFX11: v_mov_b32 v[[REG:[0-9]+]], -1
; GFX11: ; use v[[REG]]
define amdgpu_kernel void @v_input_output_i16() #0 {
%v = tail call i16 asm sideeffect "v_mov_b32 $0, -1", "=v"() #0
tail call void asm sideeffect "; use $0", "v"(i16 %v)
ret void
}

; GFX11-LABEL: {{^}}i16_imm_input_phys_vgpr:
; GFX11: v_mov_b32_e32 v0, 0xffff
; GFX11: ; use v0
define amdgpu_kernel void @i16_imm_input_phys_vgpr() {
entry:
call void asm sideeffect "; use $0 ", "{v0}"(i16 65535)
ret void
}

attributes #0 = { nounwind }
57 changes: 57 additions & 0 deletions llvm/test/CodeGen/AMDGPU/inlineasm-16-true16.ll
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@@ -0,0 +1,57 @@
; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=+real-true16 < %s | FileCheck -enable-var-scope -check-prefixes=GFX11 %s

; GFX11-LABEL: {{^}}s_input_output_i16:
; GFX11: s_mov_b32 s[[REG:[0-9]+]], -1
; GFX11: ; use s[[REG]]
define amdgpu_kernel void @s_input_output_i16() #0 {
%v = tail call i16 asm sideeffect "s_mov_b32 $0, -1", "=s"()
tail call void asm sideeffect "; use $0", "s"(i16 %v) #0
ret void
}

; GFX11-LABEL: {{^}}s_input_output_f16:
; GFX11: s_mov_b32 s[[REG:[0-9]+]], -1
; GFX11: ; use s[[REG]]
define amdgpu_kernel void @s_input_output_f16() #0 {
%v = tail call half asm sideeffect "s_mov_b32 $0, -1", "=s"() #0
tail call void asm sideeffect "; use $0", "s"(half %v)
ret void
}

; GFX11-LABEL: {{^}}v_input_output_f16:
; GFX11: v_mov_b16 v[[REG:[0-9]+.(l|h)]], -1
; GFX11: ; use v[[REG]]
define amdgpu_kernel void @v_input_output_f16() #0 {
%v = tail call half asm sideeffect "v_mov_b16 $0, -1", "=v"() #0
tail call void asm sideeffect "; use $0", "v"(half %v)
ret void
}

; GFX11-LABEL: {{^}}v_input_output_i16:
; GFX11: v_mov_b16 v[[REG:[0-9]+.(l|h)]], -1
; GFX11: ; use v[[REG]]
define amdgpu_kernel void @v_input_output_i16() #0 {
%v = tail call i16 asm sideeffect "v_mov_b16 $0, -1", "=v"() #0
tail call void asm sideeffect "; use $0", "v"(i16 %v)
ret void
}

; GFX11-LABEL: {{^}}i16_imm_input_phys_vgpr_lo:
; GFX11: v_mov_b16_e32 v0.l, -1
; GFX11: ; use v0.l
define amdgpu_kernel void @i16_imm_input_phys_vgpr_lo() {
entry:
call void asm sideeffect "; use $0 ", "{v0.l}"(i16 65535)
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@rampitec rampitec May 21, 2025

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Can you please add one more test with v0.h?

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@arsenm arsenm May 21, 2025

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And do we need a constraint to specify specifically an l or h for a virtual register?

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@broxigarchen broxigarchen May 21, 2025

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Added a .h case

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@rampitec rampitec May 21, 2025

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And do we need a constraint to specify specifically an l or h for a virtual register?

I do not think it is practically needed. At least it is not needed for correctness at this point.

ret void
}

; GFX11-LABEL: {{^}}i16_imm_input_phys_vgpr_hi:
; GFX11: v_mov_b16_e32 v0.h, -1
; GFX11: ; use v0.h
define amdgpu_kernel void @i16_imm_input_phys_vgpr_hi() {
entry:
call void asm sideeffect "; use $0 ", "{v0.h}"(i16 65535)
ret void
}

attributes #0 = { nounwind }
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