[NFC][CodeGen] Adopt MachineFunctionProperties convenience accessors

llvm/include/llvm/CodeGen/MachineFunction.h

@@ -239,6 +239,12 @@ class MachineFunctionProperties {
     return *this;
   }
 
+  // Set all the properties.
+  MachineFunctionProperties &set() {
+    Properties.set();
+    return *this;
+  }
+
   MachineFunctionProperties &set(const MachineFunctionProperties &MFP) {
     Properties |= MFP.Properties;
     return *this;

llvm/include/llvm/CodeGen/PeepholeOptimizer.h

@@ -19,8 +19,7 @@ class PeepholeOptimizerPass : public PassInfoMixin<PeepholeOptimizerPass> {
                         MachineFunctionAnalysisManager &MFAM);
 
   MachineFunctionProperties getRequiredProperties() const {
-    return MachineFunctionProperties().set(
-        MachineFunctionProperties::Property::IsSSA);
+    return MachineFunctionProperties().setIsSSA();
   }
 };
 

llvm/lib/Passes/PassBuilder.cpp

@@ -447,7 +447,7 @@ class TriggerVerifierErrorPass
     // Intentionally create a virtual register and set NoVRegs property.
     auto &MRI = MF.getRegInfo();
     MRI.createGenericVirtualRegister(LLT::scalar(8));
-    MF.getProperties().set(MachineFunctionProperties::Property::NoVRegs);
+    MF.getProperties().setNoVRegs();
     return PreservedAnalyses::all();
   }
 
@@ -465,19 +465,7 @@ class RequireAllMachineFunctionPropertiesPass
   }
 
   static MachineFunctionProperties getRequiredProperties() {
-    MachineFunctionProperties MFProps;
-    MFProps.set(MachineFunctionProperties::Property::FailedISel);
-    MFProps.set(MachineFunctionProperties::Property::FailsVerification);
-    MFProps.set(MachineFunctionProperties::Property::IsSSA);
-    MFProps.set(MachineFunctionProperties::Property::Legalized);
-    MFProps.set(MachineFunctionProperties::Property::NoPHIs);
-    MFProps.set(MachineFunctionProperties::Property::NoVRegs);
-    MFProps.set(MachineFunctionProperties::Property::RegBankSelected);
-    MFProps.set(MachineFunctionProperties::Property::Selected);
-    MFProps.set(MachineFunctionProperties::Property::TiedOpsRewritten);
-    MFProps.set(MachineFunctionProperties::Property::TracksDebugUserValues);
-    MFProps.set(MachineFunctionProperties::Property::TracksLiveness);
-    return MFProps;
+    return MachineFunctionProperties().set();
   }
   static StringRef name() { return "RequireAllMachineFunctionPropertiesPass"; }
 };

llvm/lib/Target/AArch64/AArch64A53Fix835769.cpp

@@ -86,8 +86,7 @@ class AArch64A53Fix835769 : public MachineFunctionPass {
   bool runOnMachineFunction(MachineFunction &F) override;
 
   MachineFunctionProperties getRequiredProperties() const override {
-    return MachineFunctionProperties().set(
-        MachineFunctionProperties::Property::NoVRegs);
+    return MachineFunctionProperties().setNoVRegs();
   }
 
   StringRef getPassName() const override {

llvm/lib/Target/AArch64/AArch64A57FPLoadBalancing.cpp

@@ -117,8 +117,7 @@ class AArch64A57FPLoadBalancing : public MachineFunctionPass {
   bool runOnMachineFunction(MachineFunction &F) override;
 
   MachineFunctionProperties getRequiredProperties() const override {
-    return MachineFunctionProperties().set(
-        MachineFunctionProperties::Property::NoVRegs);
+    return MachineFunctionProperties().setNoVRegs();
   }
 
   StringRef getPassName() const override {

llvm/lib/Target/AArch64/AArch64CollectLOH.cpp

@@ -132,8 +132,7 @@ struct AArch64CollectLOH : public MachineFunctionPass {
   bool runOnMachineFunction(MachineFunction &MF) override;
 
   MachineFunctionProperties getRequiredProperties() const override {
-    return MachineFunctionProperties().set(
-        MachineFunctionProperties::Property::NoVRegs);
+    return MachineFunctionProperties().setNoVRegs();
   }
 
   StringRef getPassName() const override { return AARCH64_COLLECT_LOH_NAME; }

llvm/lib/Target/AArch64/AArch64CompressJumpTables.cpp

@@ -52,8 +52,7 @@ class AArch64CompressJumpTables : public MachineFunctionPass {
   bool runOnMachineFunction(MachineFunction &MF) override;
 
   MachineFunctionProperties getRequiredProperties() const override {
-    return MachineFunctionProperties().set(
-        MachineFunctionProperties::Property::NoVRegs);
+    return MachineFunctionProperties().setNoVRegs();
   }
   StringRef getPassName() const override {
     return "AArch64 Compress Jump Tables";

llvm/lib/Target/AArch64/AArch64FalkorHWPFFix.cpp

@@ -188,8 +188,7 @@ class FalkorHWPFFix : public MachineFunctionPass {
   }
 
   MachineFunctionProperties getRequiredProperties() const override {
-    return MachineFunctionProperties().set(
-        MachineFunctionProperties::Property::NoVRegs);
+    return MachineFunctionProperties().setNoVRegs();
   }
 
 private:

llvm/lib/Target/AArch64/AArch64InstrInfo.td

@@ -1121,7 +1121,7 @@ let RecomputePerFunction = 1 in {
   // SelectionDAG's behaviour.
   // FIXME: One day there will probably be a nicer way to check for this, but
   // today is not that day.
-  def OptimizedGISelOrOtherSelector : Predicate<"!MF->getFunction().hasOptNone() || MF->getProperties().hasProperty(MachineFunctionProperties::Property::FailedISel) || !MF->getProperties().hasProperty(MachineFunctionProperties::Property::Legalized)">;
+  def OptimizedGISelOrOtherSelector : Predicate<"!MF->getFunction().hasOptNone() || MF->getProperties().hasFailedISel() || !MF->getProperties().hasLegalized()">;
 }
 
 include "AArch64InstrFormats.td"

llvm/lib/Target/AArch64/AArch64LoadStoreOptimizer.cpp

@@ -233,8 +233,7 @@ struct AArch64LoadStoreOpt : public MachineFunctionPass {
   bool runOnMachineFunction(MachineFunction &Fn) override;
 
   MachineFunctionProperties getRequiredProperties() const override {
-    return MachineFunctionProperties().set(
-        MachineFunctionProperties::Property::NoVRegs);
+    return MachineFunctionProperties().setNoVRegs();
   }
 
   StringRef getPassName() const override { return AARCH64_LOAD_STORE_OPT_NAME; }

llvm/lib/Target/AArch64/AArch64LowerHomogeneousPrologEpilog.cpp

@@ -173,9 +173,7 @@ static MachineFunction &createFrameHelperMachineFunction(Module *M,
 
   MachineFunction &MF = MMI->getOrCreateMachineFunction(*F);
   // Remove unnecessary register liveness and set NoVRegs.
-  MF.getProperties().reset(MachineFunctionProperties::Property::TracksLiveness);
-  MF.getProperties().reset(MachineFunctionProperties::Property::IsSSA);
-  MF.getProperties().set(MachineFunctionProperties::Property::NoVRegs);
+  MF.getProperties().resetTracksLiveness().resetIsSSA().setNoVRegs();
   MF.getRegInfo().freezeReservedRegs();
 
   // Create entry block.

llvm/lib/Target/AArch64/AArch64RedundantCopyElimination.cpp

@@ -92,8 +92,7 @@ class AArch64RedundantCopyElimination : public MachineFunctionPass {
   bool optimizeBlock(MachineBasicBlock *MBB);
   bool runOnMachineFunction(MachineFunction &MF) override;
   MachineFunctionProperties getRequiredProperties() const override {
-    return MachineFunctionProperties().set(
-        MachineFunctionProperties::Property::NoVRegs);
+    return MachineFunctionProperties().setNoVRegs();
   }
   StringRef getPassName() const override {
     return "AArch64 Redundant Copy Elimination";

llvm/lib/Target/AArch64/AArch64RegisterInfo.cpp

@@ -544,8 +544,7 @@ AArch64RegisterInfo::getReservedRegs(const MachineFunction &MF) const {
     // the pipeline since it prevents other infrastructure from reasoning about
     // it's liveness. We use the NoVRegs property instead of IsSSA because
     // IsSSA is removed before VirtRegRewriter runs.
-    if (!MF.getProperties().hasProperty(
-            MachineFunctionProperties::Property::NoVRegs))
+    if (!MF.getProperties().hasNoVRegs())
       markSuperRegs(Reserved, AArch64::LR);
   }
 

llvm/lib/Target/AArch64/GISel/AArch64O0PreLegalizerCombiner.cpp

@@ -147,8 +147,7 @@ AArch64O0PreLegalizerCombiner::AArch64O0PreLegalizerCombiner()
 }
 
 bool AArch64O0PreLegalizerCombiner::runOnMachineFunction(MachineFunction &MF) {
-  if (MF.getProperties().hasProperty(
-          MachineFunctionProperties::Property::FailedISel))
+  if (MF.getProperties().hasFailedISel())
     return false;
   auto &TPC = getAnalysis<TargetPassConfig>();
 

llvm/lib/Target/AArch64/GISel/AArch64PostLegalizerCombiner.cpp

@@ -654,12 +654,9 @@ AArch64PostLegalizerCombiner::AArch64PostLegalizerCombiner(bool IsOptNone)
 }
 
 bool AArch64PostLegalizerCombiner::runOnMachineFunction(MachineFunction &MF) {
-  if (MF.getProperties().hasProperty(
-          MachineFunctionProperties::Property::FailedISel))
+  if (MF.getProperties().hasFailedISel())
     return false;
-  assert(MF.getProperties().hasProperty(
-             MachineFunctionProperties::Property::Legalized) &&
-         "Expected a legalized function?");
+  assert(MF.getProperties().hasLegalized() && "Expected a legalized function?");
   auto *TPC = &getAnalysis<TargetPassConfig>();
   const Function &F = MF.getFunction();
   bool EnableOpt =

llvm/lib/Target/AArch64/GISel/AArch64PostLegalizerLowering.cpp

@@ -1257,12 +1257,9 @@ AArch64PostLegalizerLowering::AArch64PostLegalizerLowering()
 }
 
 bool AArch64PostLegalizerLowering::runOnMachineFunction(MachineFunction &MF) {
-  if (MF.getProperties().hasProperty(
-          MachineFunctionProperties::Property::FailedISel))
+  if (MF.getProperties().hasFailedISel())
     return false;
-  assert(MF.getProperties().hasProperty(
-             MachineFunctionProperties::Property::Legalized) &&
-         "Expected a legalized function?");
+  assert(MF.getProperties().hasLegalized() && "Expected a legalized function?");
   auto *TPC = &getAnalysis<TargetPassConfig>();
   const Function &F = MF.getFunction();
 

llvm/lib/Target/AArch64/GISel/AArch64PostSelectOptimize.cpp

@@ -292,12 +292,9 @@ bool AArch64PostSelectOptimize::optimizeNZCVDefs(MachineBasicBlock &MBB) {
 }
 
 bool AArch64PostSelectOptimize::runOnMachineFunction(MachineFunction &MF) {
-  if (MF.getProperties().hasProperty(
-          MachineFunctionProperties::Property::FailedISel))
+  if (MF.getProperties().hasFailedISel())
     return false;
-  assert(MF.getProperties().hasProperty(
-             MachineFunctionProperties::Property::Selected) &&
-         "Expected a selected MF");
+  assert(MF.getProperties().hasSelected() && "Expected a selected MF");
 
   bool Changed = false;
   for (auto &BB : MF) {

llvm/lib/Target/AArch64/GISel/AArch64PreLegalizerCombiner.cpp

@@ -836,8 +836,7 @@ AArch64PreLegalizerCombiner::AArch64PreLegalizerCombiner()
 }
 
 bool AArch64PreLegalizerCombiner::runOnMachineFunction(MachineFunction &MF) {
-  if (MF.getProperties().hasProperty(
-          MachineFunctionProperties::Property::FailedISel))
+  if (MF.getProperties().hasFailedISel())
     return false;
   auto &TPC = getAnalysis<TargetPassConfig>();
 

llvm/lib/Target/AMDGPU/AMDGPUPostLegalizerCombiner.cpp

@@ -478,8 +478,7 @@ AMDGPUPostLegalizerCombiner::AMDGPUPostLegalizerCombiner(bool IsOptNone)
 }
 
 bool AMDGPUPostLegalizerCombiner::runOnMachineFunction(MachineFunction &MF) {
-  if (MF.getProperties().hasProperty(
-          MachineFunctionProperties::Property::FailedISel))
+  if (MF.getProperties().hasFailedISel())
     return false;
   auto *TPC = &getAnalysis<TargetPassConfig>();
   const Function &F = MF.getFunction();

llvm/lib/Target/AMDGPU/AMDGPUPreLegalizerCombiner.cpp

@@ -253,8 +253,7 @@ AMDGPUPreLegalizerCombiner::AMDGPUPreLegalizerCombiner(bool IsOptNone)
 }
 
 bool AMDGPUPreLegalizerCombiner::runOnMachineFunction(MachineFunction &MF) {
-  if (MF.getProperties().hasProperty(
-          MachineFunctionProperties::Property::FailedISel))
+  if (MF.getProperties().hasFailedISel())
     return false;
   auto *TPC = &getAnalysis<TargetPassConfig>();
   const Function &F = MF.getFunction();

llvm/lib/Target/AMDGPU/AMDGPURegBankCombiner.cpp

@@ -462,8 +462,7 @@ AMDGPURegBankCombiner::AMDGPURegBankCombiner(bool IsOptNone)
 }
 
 bool AMDGPURegBankCombiner::runOnMachineFunction(MachineFunction &MF) {
-  if (MF.getProperties().hasProperty(
-          MachineFunctionProperties::Property::FailedISel))
+  if (MF.getProperties().hasFailedISel())
     return false;
   auto *TPC = &getAnalysis<TargetPassConfig>();
   const Function &F = MF.getFunction();

llvm/lib/Target/AMDGPU/AMDGPURegBankLegalize.cpp

@@ -58,8 +58,7 @@ class AMDGPURegBankLegalize : public MachineFunctionPass {
   // If there were no phis and we do waterfall expansion machine verifier would
   // fail.
   MachineFunctionProperties getClearedProperties() const override {
-    return MachineFunctionProperties().set(
-        MachineFunctionProperties::Property::NoPHIs);
+    return MachineFunctionProperties().setNoPHIs();
   }
 };
 
@@ -250,8 +249,7 @@ class AMDGPURegBankLegalizeCombiner {
 }
 
 bool AMDGPURegBankLegalize::runOnMachineFunction(MachineFunction &MF) {
-  if (MF.getProperties().hasProperty(
-          MachineFunctionProperties::Property::FailedISel))
+  if (MF.getProperties().hasFailedISel())
     return false;
 
   // Setup the instruction builder with CSE.

llvm/lib/Target/AMDGPU/AMDGPURegBankSelect.cpp

@@ -53,8 +53,7 @@ class AMDGPURegBankSelect : public MachineFunctionPass {
   // This pass assigns register banks to all virtual registers, and we maintain
   // this property in subsequent passes
   MachineFunctionProperties getSetProperties() const override {
-    return MachineFunctionProperties().set(
-        MachineFunctionProperties::Property::RegBankSelected);
+    return MachineFunctionProperties().setRegBankSelected();
   }
 };
 
@@ -199,8 +198,7 @@ static Register getVReg(MachineOperand &Op) {
 }
 
 bool AMDGPURegBankSelect::runOnMachineFunction(MachineFunction &MF) {
-  if (MF.getProperties().hasProperty(
-          MachineFunctionProperties::Property::FailedISel))
+  if (MF.getProperties().hasFailedISel())
     return false;
 
   // Setup the instruction builder with CSE.

llvm/lib/Target/AMDGPU/GCNDPPCombine.cpp

@@ -98,8 +98,7 @@ class GCNDPPCombineLegacy : public MachineFunctionPass {
   }
 
   MachineFunctionProperties getRequiredProperties() const override {
-    return MachineFunctionProperties()
-      .set(MachineFunctionProperties::Property::IsSSA);
+    return MachineFunctionProperties().setIsSSA();
   }
 };
 

llvm/lib/Target/AMDGPU/GCNDPPCombine.h

@@ -18,8 +18,7 @@ class GCNDPPCombinePass : public PassInfoMixin<GCNDPPCombinePass> {
                         MachineFunctionAnalysisManager &MAM);
 
   MachineFunctionProperties getRequiredProperties() const {
-    return MachineFunctionProperties().set(
-        MachineFunctionProperties::Property::IsSSA);
+    return MachineFunctionProperties().setIsSSA();
   }
 };
 

llvm/lib/Target/AMDGPU/R600MachineCFGStructurizer.cpp

@@ -121,8 +121,7 @@ class R600MachineCFGStructurizer : public MachineFunctionPass {
 
   bool runOnMachineFunction(MachineFunction &MF) override {
     // FIXME: This pass causes verification failures.
-    MF.getProperties().set(
-        MachineFunctionProperties::Property::FailsVerification);
+    MF.getProperties().setFailsVerification();
 
     TII = MF.getSubtarget<R600Subtarget>().getInstrInfo();
     TRI = &TII->getRegisterInfo();

llvm/lib/Target/AMDGPU/R600OptimizeVectorRegisters.cpp

@@ -111,8 +111,7 @@ class R600VectorRegMerger : public MachineFunctionPass {
   }
 
   MachineFunctionProperties getRequiredProperties() const override {
-    return MachineFunctionProperties()
-      .set(MachineFunctionProperties::Property::IsSSA);
+    return MachineFunctionProperties().setIsSSA();
   }
 
   StringRef getPassName() const override {

llvm/lib/Target/AMDGPU/SIFixSGPRCopies.cpp

@@ -618,8 +618,7 @@ static bool hoistAndMergeSGPRInits(unsigned Reg,
 
 bool SIFixSGPRCopies::run(MachineFunction &MF) {
   // Only need to run this in SelectionDAG path.
-  if (MF.getProperties().hasProperty(
-        MachineFunctionProperties::Property::Selected))
+  if (MF.getProperties().hasSelected())
     return false;
 
   const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>();

llvm/lib/Target/AMDGPU/SIFoldOperands.cpp

@@ -191,8 +191,7 @@ class SIFoldOperandsLegacy : public MachineFunctionPass {
   }
 
   MachineFunctionProperties getRequiredProperties() const override {
-    return MachineFunctionProperties().set(
-        MachineFunctionProperties::Property::IsSSA);
+    return MachineFunctionProperties().setIsSSA();
   }
 };
 

llvm/lib/Target/AMDGPU/SIFoldOperands.h

@@ -19,8 +19,7 @@ class SIFoldOperandsPass : public PassInfoMixin<SIFoldOperandsPass> {
                         MachineFunctionAnalysisManager &MFAM);
 
   MachineFunctionProperties getRequiredProperties() const {
-    return MachineFunctionProperties().set(
-        MachineFunctionProperties::Property::IsSSA);
+    return MachineFunctionProperties().setIsSSA();
   }
 };
 } // namespace llvm

llvm/lib/Target/AMDGPU/SIFormMemoryClauses.cpp

@@ -78,8 +78,7 @@ class SIFormMemoryClausesLegacy : public MachineFunctionPass {
   }
 
   MachineFunctionProperties getClearedProperties() const override {
-    return MachineFunctionProperties().set(
-        MachineFunctionProperties::Property::IsSSA);
+    return MachineFunctionProperties().setIsSSA();
   }
 };
 

llvm/lib/Target/AMDGPU/SILoadStoreOptimizer.cpp

@@ -323,8 +323,7 @@ class SILoadStoreOptimizerLegacy : public MachineFunctionPass {
   }
 
   MachineFunctionProperties getRequiredProperties() const override {
-    return MachineFunctionProperties()
-      .set(MachineFunctionProperties::Property::IsSSA);
+    return MachineFunctionProperties().setIsSSA();
   }
 };
 

llvm/lib/Target/AMDGPU/SILoadStoreOptimizer.h

@@ -20,8 +20,7 @@ class SILoadStoreOptimizerPass
                         MachineFunctionAnalysisManager &MFAM);
 
   MachineFunctionProperties getRequiredProperties() const {
-    return MachineFunctionProperties().set(
-        MachineFunctionProperties::Property::IsSSA);
+    return MachineFunctionProperties().setIsSSA();
   }
 };
 

llvm/lib/Target/AMDGPU/SILowerI1Copies.cpp

@@ -859,8 +859,7 @@ void Vreg1LoweringHelper::constrainAsLaneMask(Incoming &In) {}
 static bool runFixI1Copies(MachineFunction &MF, MachineDominatorTree &MDT,
                            MachinePostDominatorTree &MPDT) {
   // Only need to run this in SelectionDAG path.
-  if (MF.getProperties().hasProperty(
-          MachineFunctionProperties::Property::Selected))
+  if (MF.getProperties().hasSelected())
     return false;
 
   Vreg1LoweringHelper Helper(&MF, &MDT, &MPDT);