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[AMDGPU][True16][CodeGen] v_s_xxx_f16 t16 mode handling in movetoVALU process #141152

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Merged
merged 2 commits into from
Jun 10, 2025
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[AMDGPU][True16][CodeGen] v_s_xxx_f16 t16 mode handling in movetoVALU process #141152

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231edfd
v_s_xx_f16 support in moveToVALU
broxigarchen May 22, 2025
7c75502
fix an error
broxigarchen Jun 10, 2025
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23 changes: 23 additions & 0 deletions llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -7734,6 +7734,29 @@ void SIInstrInfo::moveToVALUImpl(SIInstrWorklist &Worklist,
Inst.eraseFromParent();
return;
}
case AMDGPU::V_S_EXP_F16_e64:
case AMDGPU::V_S_LOG_F16_e64:
case AMDGPU::V_S_RCP_F16_e64:
case AMDGPU::V_S_RSQ_F16_e64:
case AMDGPU::V_S_SQRT_F16_e64: {
const DebugLoc &DL = Inst.getDebugLoc();
Register NewDst = MRI.createVirtualRegister(ST.useRealTrue16Insts()
? &AMDGPU::VGPR_16RegClass
: &AMDGPU::VGPR_32RegClass);
auto NewInstr = BuildMI(*MBB, Inst, DL, get(NewOpcode), NewDst)
.addImm(0) // src0_modifiers
.add(Inst.getOperand(2))
.addImm(0) // clamp
.addImm(0); // omod
if (ST.useRealTrue16Insts())
NewInstr.addImm(0); // opsel0
MRI.replaceRegWith(Inst.getOperand(0).getReg(), NewDst);
legalizeOperandsVALUt16(*NewInstr, MRI);
legalizeOperands(*NewInstr, MDT);
addUsersToMoveToVALUWorklist(NewDst, MRI, Worklist);
Inst.eraseFromParent();
return;
}
}

if (NewOpcode == AMDGPU::INSTRUCTION_LIST_END) {
Expand Down
893 changes: 893 additions & 0 deletions llvm/test/CodeGen/AMDGPU/frem.ll
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101 changes: 94 additions & 7 deletions llvm/test/CodeGen/AMDGPU/llvm.amdgcn.rcp.f16.ll
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Original file line number Diff line number Diff line change
@@ -1,17 +1,102 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
; RUN: llc -mtriple=amdgcn -mcpu=fiji -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=VI %s
; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=-flat-for-global,+real-true16 -verify-machineinstrs < %s | FileCheck -check-prefix=GFX11-TRUE16 %s
; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=-flat-for-global,-real-true16 -verify-machineinstrs < %s | FileCheck -check-prefix=GFX11-FAKE16 %s
; RUN: llc -mtriple=amdgcn -mcpu=gfx1200 -mattr=-flat-for-global,+real-true16 -verify-machineinstrs < %s | FileCheck -check-prefix=GFX12-TRUE16 %s
; RUN: llc -mtriple=amdgcn -mcpu=gfx1200 -mattr=-flat-for-global,-real-true16 -verify-machineinstrs < %s | FileCheck -check-prefix=GFX12-FAKE16 %s

declare half @llvm.amdgcn.rcp.f16(half %a)

; GCN-LABEL: {{^}}rcp_f16
; GCN: buffer_load_ushort v[[A_F16:[0-9]+]]
; VI: v_rcp_f16_e32 v[[R_F16:[0-9]+]], v[[A_F16]]
; GFX11-TRUE16: v_rcp_f16_e32 v[[A_F16:[0-9]+]].l, v[[A_F16]].l
; GFX11-FAKE16: v_rcp_f16_e32 v[[A_F16:[0-9]+]], v[[A_F16]]
; GCN: buffer_store_short v[[R_F16]]
; GCN: s_endpgm
define amdgpu_kernel void @rcp_f16(
; GCN-LABEL: rcp_f16:
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@Sisyph Sisyph Jun 10, 2025

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Needs a rerun. No run line with GCN, and no check with VI

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@broxigarchen broxigarchen Jun 10, 2025 •
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Oh, the GCN and VI are in the same runline -check-prefix=GCN -check-prefix=VI

All test has been updated with script

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Oh, does that work? Looks like it would work here, but then whats the difference between that and check-prefixes

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@broxigarchen broxigarchen Jun 10, 2025 •
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Not sure if there are corner cases, -check-prefix=a -check-prefix=b seems to work samely as -check-prefixes=a,b.

; GCN: ; %bb.0: ; %entry
; GCN-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
; GCN-NEXT: s_mov_b32 s7, 0xf000
; GCN-NEXT: s_mov_b32 s6, -1
; GCN-NEXT: s_mov_b32 s10, s6
; GCN-NEXT: s_mov_b32 s11, s7
; GCN-NEXT: s_waitcnt lgkmcnt(0)
; GCN-NEXT: s_mov_b32 s8, s2
; GCN-NEXT: s_mov_b32 s9, s3
; GCN-NEXT: buffer_load_ushort v0, off, s[8:11], 0
; GCN-NEXT: s_mov_b32 s4, s0
; GCN-NEXT: s_mov_b32 s5, s1
; GCN-NEXT: s_waitcnt vmcnt(0)
; GCN-NEXT: v_rcp_f16_e32 v0, v0
; GCN-NEXT: buffer_store_short v0, off, s[4:7], 0
; GCN-NEXT: s_endpgm
;
; GFX11-TRUE16-LABEL: rcp_f16:
; GFX11-TRUE16: ; %bb.0: ; %entry
; GFX11-TRUE16-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
; GFX11-TRUE16-NEXT: s_mov_b32 s6, -1
; GFX11-TRUE16-NEXT: s_mov_b32 s7, 0x31016000
; GFX11-TRUE16-NEXT: s_mov_b32 s10, s6
; GFX11-TRUE16-NEXT: s_mov_b32 s11, s7
; GFX11-TRUE16-NEXT: s_waitcnt lgkmcnt(0)
; GFX11-TRUE16-NEXT: s_mov_b32 s8, s2
; GFX11-TRUE16-NEXT: s_mov_b32 s9, s3
; GFX11-TRUE16-NEXT: s_mov_b32 s4, s0
; GFX11-TRUE16-NEXT: buffer_load_u16 v0, off, s[8:11], 0
; GFX11-TRUE16-NEXT: s_mov_b32 s5, s1
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
; GFX11-TRUE16-NEXT: v_rcp_f16_e32 v0.l, v0.l
; GFX11-TRUE16-NEXT: buffer_store_b16 v0, off, s[4:7], 0
; GFX11-TRUE16-NEXT: s_endpgm
;
; GFX11-FAKE16-LABEL: rcp_f16:
; GFX11-FAKE16: ; %bb.0: ; %entry
; GFX11-FAKE16-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
; GFX11-FAKE16-NEXT: s_mov_b32 s6, -1
; GFX11-FAKE16-NEXT: s_mov_b32 s7, 0x31016000
; GFX11-FAKE16-NEXT: s_mov_b32 s10, s6
; GFX11-FAKE16-NEXT: s_mov_b32 s11, s7
; GFX11-FAKE16-NEXT: s_waitcnt lgkmcnt(0)
; GFX11-FAKE16-NEXT: s_mov_b32 s8, s2
; GFX11-FAKE16-NEXT: s_mov_b32 s9, s3
; GFX11-FAKE16-NEXT: s_mov_b32 s4, s0
; GFX11-FAKE16-NEXT: buffer_load_u16 v0, off, s[8:11], 0
; GFX11-FAKE16-NEXT: s_mov_b32 s5, s1
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0)
; GFX11-FAKE16-NEXT: v_rcp_f16_e32 v0, v0
; GFX11-FAKE16-NEXT: buffer_store_b16 v0, off, s[4:7], 0
; GFX11-FAKE16-NEXT: s_endpgm
;
; GFX12-TRUE16-LABEL: rcp_f16:
; GFX12-TRUE16: ; %bb.0: ; %entry
; GFX12-TRUE16-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
; GFX12-TRUE16-NEXT: s_mov_b32 s6, -1
; GFX12-TRUE16-NEXT: s_mov_b32 s7, 0x31016000
; GFX12-TRUE16-NEXT: s_mov_b32 s10, s6
; GFX12-TRUE16-NEXT: s_mov_b32 s11, s7
; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0
; GFX12-TRUE16-NEXT: s_mov_b32 s8, s2
; GFX12-TRUE16-NEXT: s_mov_b32 s9, s3
; GFX12-TRUE16-NEXT: s_mov_b32 s4, s0
; GFX12-TRUE16-NEXT: buffer_load_u16 v0, off, s[8:11], null
; GFX12-TRUE16-NEXT: s_mov_b32 s5, s1
; GFX12-TRUE16-NEXT: s_wait_loadcnt 0x0
; GFX12-TRUE16-NEXT: v_rcp_f16_e32 v0.l, v0.l
; GFX12-TRUE16-NEXT: buffer_store_b16 v0, off, s[4:7], null
; GFX12-TRUE16-NEXT: s_endpgm
;
; GFX12-FAKE16-LABEL: rcp_f16:
; GFX12-FAKE16: ; %bb.0: ; %entry
; GFX12-FAKE16-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
; GFX12-FAKE16-NEXT: s_mov_b32 s6, -1
; GFX12-FAKE16-NEXT: s_mov_b32 s7, 0x31016000
; GFX12-FAKE16-NEXT: s_mov_b32 s10, s6
; GFX12-FAKE16-NEXT: s_mov_b32 s11, s7
; GFX12-FAKE16-NEXT: s_wait_kmcnt 0x0
; GFX12-FAKE16-NEXT: s_mov_b32 s8, s2
; GFX12-FAKE16-NEXT: s_mov_b32 s9, s3
; GFX12-FAKE16-NEXT: s_mov_b32 s4, s0
; GFX12-FAKE16-NEXT: buffer_load_u16 v0, off, s[8:11], null
; GFX12-FAKE16-NEXT: s_mov_b32 s5, s1
; GFX12-FAKE16-NEXT: s_wait_loadcnt 0x0
; GFX12-FAKE16-NEXT: v_rcp_f16_e32 v0, v0
; GFX12-FAKE16-NEXT: buffer_store_b16 v0, off, s[4:7], null
; GFX12-FAKE16-NEXT: s_endpgm
ptr addrspace(1) %r,
ptr addrspace(1) %a) {
entry:
Expand All @@ -20,3 +105,5 @@ entry:
store half %r.val, ptr addrspace(1) %r
ret void
}
;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
; VI: {{.*}}
101 changes: 94 additions & 7 deletions llvm/test/CodeGen/AMDGPU/llvm.amdgcn.rsq.f16.ll
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Original file line number Diff line number Diff line change
@@ -1,17 +1,102 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
; RUN: llc -mtriple=amdgcn -mcpu=fiji -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=VI %s
; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=-flat-for-global,+real-true16 -verify-machineinstrs < %s | FileCheck -check-prefix=GFX11-TRUE16 %s
; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=-flat-for-global,-real-true16 -verify-machineinstrs < %s | FileCheck -check-prefix=GFX11-FAKE16 %s
; RUN: llc -mtriple=amdgcn -mcpu=gfx1200 -mattr=-flat-for-global,+real-true16 -verify-machineinstrs < %s | FileCheck -check-prefix=GFX12-TRUE16 %s
; RUN: llc -mtriple=amdgcn -mcpu=gfx1200 -mattr=-flat-for-global,-real-true16 -verify-machineinstrs < %s | FileCheck -check-prefix=GFX12-FAKE16 %s

declare half @llvm.amdgcn.rsq.f16(half %a)

; GCN-LABEL: {{^}}rsq_f16
; GCN: buffer_load_ushort v[[A_F16:[0-9]+]]
; VI: v_rsq_f16_e32 v[[R_F16:[0-9]+]], v[[A_F16]]
; GFX11-TRUE16: v_rsq_f16_e32 v[[A_F16:[0-9]+]].l, v[[A_F16]].l
; GFX11-FAKE16: v_rsq_f16_e32 v[[A_F16:[0-9]+]], v[[A_F16]]
; GCN: buffer_store_short v[[R_F16]]
; GCN: s_endpgm
define amdgpu_kernel void @rsq_f16(
; GCN-LABEL: rsq_f16:
; GCN: ; %bb.0: ; %entry
; GCN-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
; GCN-NEXT: s_mov_b32 s7, 0xf000
; GCN-NEXT: s_mov_b32 s6, -1
; GCN-NEXT: s_mov_b32 s10, s6
; GCN-NEXT: s_mov_b32 s11, s7
; GCN-NEXT: s_waitcnt lgkmcnt(0)
; GCN-NEXT: s_mov_b32 s8, s2
; GCN-NEXT: s_mov_b32 s9, s3
; GCN-NEXT: buffer_load_ushort v0, off, s[8:11], 0
; GCN-NEXT: s_mov_b32 s4, s0
; GCN-NEXT: s_mov_b32 s5, s1
; GCN-NEXT: s_waitcnt vmcnt(0)
; GCN-NEXT: v_rsq_f16_e32 v0, v0
; GCN-NEXT: buffer_store_short v0, off, s[4:7], 0
; GCN-NEXT: s_endpgm
;
; GFX11-TRUE16-LABEL: rsq_f16:
; GFX11-TRUE16: ; %bb.0: ; %entry
; GFX11-TRUE16-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
; GFX11-TRUE16-NEXT: s_mov_b32 s6, -1
; GFX11-TRUE16-NEXT: s_mov_b32 s7, 0x31016000
; GFX11-TRUE16-NEXT: s_mov_b32 s10, s6
; GFX11-TRUE16-NEXT: s_mov_b32 s11, s7
; GFX11-TRUE16-NEXT: s_waitcnt lgkmcnt(0)
; GFX11-TRUE16-NEXT: s_mov_b32 s8, s2
; GFX11-TRUE16-NEXT: s_mov_b32 s9, s3
; GFX11-TRUE16-NEXT: s_mov_b32 s4, s0
; GFX11-TRUE16-NEXT: buffer_load_u16 v0, off, s[8:11], 0
; GFX11-TRUE16-NEXT: s_mov_b32 s5, s1
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
; GFX11-TRUE16-NEXT: v_rsq_f16_e32 v0.l, v0.l
; GFX11-TRUE16-NEXT: buffer_store_b16 v0, off, s[4:7], 0
; GFX11-TRUE16-NEXT: s_endpgm
;
; GFX11-FAKE16-LABEL: rsq_f16:
; GFX11-FAKE16: ; %bb.0: ; %entry
; GFX11-FAKE16-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
; GFX11-FAKE16-NEXT: s_mov_b32 s6, -1
; GFX11-FAKE16-NEXT: s_mov_b32 s7, 0x31016000
; GFX11-FAKE16-NEXT: s_mov_b32 s10, s6
; GFX11-FAKE16-NEXT: s_mov_b32 s11, s7
; GFX11-FAKE16-NEXT: s_waitcnt lgkmcnt(0)
; GFX11-FAKE16-NEXT: s_mov_b32 s8, s2
; GFX11-FAKE16-NEXT: s_mov_b32 s9, s3
; GFX11-FAKE16-NEXT: s_mov_b32 s4, s0
; GFX11-FAKE16-NEXT: buffer_load_u16 v0, off, s[8:11], 0
; GFX11-FAKE16-NEXT: s_mov_b32 s5, s1
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0)
; GFX11-FAKE16-NEXT: v_rsq_f16_e32 v0, v0
; GFX11-FAKE16-NEXT: buffer_store_b16 v0, off, s[4:7], 0
; GFX11-FAKE16-NEXT: s_endpgm
;
; GFX12-TRUE16-LABEL: rsq_f16:
; GFX12-TRUE16: ; %bb.0: ; %entry
; GFX12-TRUE16-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
; GFX12-TRUE16-NEXT: s_mov_b32 s6, -1
; GFX12-TRUE16-NEXT: s_mov_b32 s7, 0x31016000
; GFX12-TRUE16-NEXT: s_mov_b32 s10, s6
; GFX12-TRUE16-NEXT: s_mov_b32 s11, s7
; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0
; GFX12-TRUE16-NEXT: s_mov_b32 s8, s2
; GFX12-TRUE16-NEXT: s_mov_b32 s9, s3
; GFX12-TRUE16-NEXT: s_mov_b32 s4, s0
; GFX12-TRUE16-NEXT: buffer_load_u16 v0, off, s[8:11], null
; GFX12-TRUE16-NEXT: s_mov_b32 s5, s1
; GFX12-TRUE16-NEXT: s_wait_loadcnt 0x0
; GFX12-TRUE16-NEXT: v_rsq_f16_e32 v0.l, v0.l
; GFX12-TRUE16-NEXT: buffer_store_b16 v0, off, s[4:7], null
; GFX12-TRUE16-NEXT: s_endpgm
;
; GFX12-FAKE16-LABEL: rsq_f16:
; GFX12-FAKE16: ; %bb.0: ; %entry
; GFX12-FAKE16-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
; GFX12-FAKE16-NEXT: s_mov_b32 s6, -1
; GFX12-FAKE16-NEXT: s_mov_b32 s7, 0x31016000
; GFX12-FAKE16-NEXT: s_mov_b32 s10, s6
; GFX12-FAKE16-NEXT: s_mov_b32 s11, s7
; GFX12-FAKE16-NEXT: s_wait_kmcnt 0x0
; GFX12-FAKE16-NEXT: s_mov_b32 s8, s2
; GFX12-FAKE16-NEXT: s_mov_b32 s9, s3
; GFX12-FAKE16-NEXT: s_mov_b32 s4, s0
; GFX12-FAKE16-NEXT: buffer_load_u16 v0, off, s[8:11], null
; GFX12-FAKE16-NEXT: s_mov_b32 s5, s1
; GFX12-FAKE16-NEXT: s_wait_loadcnt 0x0
; GFX12-FAKE16-NEXT: v_rsq_f16_e32 v0, v0
; GFX12-FAKE16-NEXT: buffer_store_b16 v0, off, s[4:7], null
; GFX12-FAKE16-NEXT: s_endpgm
ptr addrspace(1) %r,
ptr addrspace(1) %a) {
entry:
Expand All @@ -20,3 +105,5 @@ entry:
store half %r.val, ptr addrspace(1) %r
ret void
}
;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
; VI: {{.*}}
88 changes: 84 additions & 4 deletions llvm/test/CodeGen/AMDGPU/llvm.sqrt.f16.ll
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Original file line number Diff line number Diff line change
@@ -1,8 +1,10 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
; RUN: llc -amdgpu-scalarize-global-loads=false -mtriple=amdgcn -mcpu=tahiti -verify-machineinstrs < %s | FileCheck -check-prefixes=SI %s
; RUN: llc -amdgpu-scalarize-global-loads=false -mtriple=amdgcn -mcpu=fiji -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefixes=VI %s
; RUN: llc -amdgpu-scalarize-global-loads=false -mtriple=amdgcn -mcpu=gfx1100 -mattr=+real-true16 -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX11,GFX11-TRUE16 %s
; RUN: llc -amdgpu-scalarize-global-loads=false -mtriple=amdgcn -mcpu=gfx1100 -mattr=-real-true16 -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX11,GFX11-FAKE16 %s
; RUN: llc -amdgpu-scalarize-global-loads=false -mtriple=amdgcn -mcpu=gfx1100 -mattr=+real-true16 -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX11-TRUE16 %s
; RUN: llc -amdgpu-scalarize-global-loads=false -mtriple=amdgcn -mcpu=gfx1100 -mattr=-real-true16 -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX11-FAKE16 %s
; RUN: llc -amdgpu-scalarize-global-loads=false -mtriple=amdgcn -mcpu=gfx1200 -mattr=+real-true16 -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX12-TRUE16 %s
; RUN: llc -amdgpu-scalarize-global-loads=false -mtriple=amdgcn -mcpu=gfx1200 -mattr=-real-true16 -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX12-FAKE16 %s

declare half @llvm.sqrt.f16(half %a)
declare <2 x half> @llvm.sqrt.v2f16(<2 x half> %a)
Expand Down Expand Up @@ -81,6 +83,42 @@ define amdgpu_kernel void @sqrt_f16(
; GFX11-FAKE16-NEXT: v_sqrt_f16_e32 v0, v0
; GFX11-FAKE16-NEXT: buffer_store_b16 v0, off, s[4:7], 0
; GFX11-FAKE16-NEXT: s_endpgm
;
; GFX12-TRUE16-LABEL: sqrt_f16:
; GFX12-TRUE16: ; %bb.0: ; %entry
; GFX12-TRUE16-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
; GFX12-TRUE16-NEXT: s_mov_b32 s6, -1
; GFX12-TRUE16-NEXT: s_mov_b32 s7, 0x31016000
; GFX12-TRUE16-NEXT: s_mov_b32 s10, s6
; GFX12-TRUE16-NEXT: s_mov_b32 s11, s7
; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0
; GFX12-TRUE16-NEXT: s_mov_b32 s8, s2
; GFX12-TRUE16-NEXT: s_mov_b32 s9, s3
; GFX12-TRUE16-NEXT: s_mov_b32 s4, s0
; GFX12-TRUE16-NEXT: buffer_load_u16 v0, off, s[8:11], null
; GFX12-TRUE16-NEXT: s_mov_b32 s5, s1
; GFX12-TRUE16-NEXT: s_wait_loadcnt 0x0
; GFX12-TRUE16-NEXT: v_sqrt_f16_e32 v0.l, v0.l
; GFX12-TRUE16-NEXT: buffer_store_b16 v0, off, s[4:7], null
; GFX12-TRUE16-NEXT: s_endpgm
;
; GFX12-FAKE16-LABEL: sqrt_f16:
; GFX12-FAKE16: ; %bb.0: ; %entry
; GFX12-FAKE16-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
; GFX12-FAKE16-NEXT: s_mov_b32 s6, -1
; GFX12-FAKE16-NEXT: s_mov_b32 s7, 0x31016000
; GFX12-FAKE16-NEXT: s_mov_b32 s10, s6
; GFX12-FAKE16-NEXT: s_mov_b32 s11, s7
; GFX12-FAKE16-NEXT: s_wait_kmcnt 0x0
; GFX12-FAKE16-NEXT: s_mov_b32 s8, s2
; GFX12-FAKE16-NEXT: s_mov_b32 s9, s3
; GFX12-FAKE16-NEXT: s_mov_b32 s4, s0
; GFX12-FAKE16-NEXT: buffer_load_u16 v0, off, s[8:11], null
; GFX12-FAKE16-NEXT: s_mov_b32 s5, s1
; GFX12-FAKE16-NEXT: s_wait_loadcnt 0x0
; GFX12-FAKE16-NEXT: v_sqrt_f16_e32 v0, v0
; GFX12-FAKE16-NEXT: buffer_store_b16 v0, off, s[4:7], null
; GFX12-FAKE16-NEXT: s_endpgm
ptr addrspace(1) %r,
ptr addrspace(1) %a) {
entry:
Expand Down Expand Up @@ -189,6 +227,50 @@ define amdgpu_kernel void @sqrt_v2f16(
; GFX11-FAKE16-NEXT: v_pack_b32_f16 v0, v0, v1
; GFX11-FAKE16-NEXT: buffer_store_b32 v0, off, s[4:7], 0
; GFX11-FAKE16-NEXT: s_endpgm
;
; GFX12-TRUE16-LABEL: sqrt_v2f16:
; GFX12-TRUE16: ; %bb.0: ; %entry
; GFX12-TRUE16-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
; GFX12-TRUE16-NEXT: s_mov_b32 s6, -1
; GFX12-TRUE16-NEXT: s_mov_b32 s7, 0x31016000
; GFX12-TRUE16-NEXT: s_mov_b32 s10, s6
; GFX12-TRUE16-NEXT: s_mov_b32 s11, s7
; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0
; GFX12-TRUE16-NEXT: s_mov_b32 s8, s2
; GFX12-TRUE16-NEXT: s_mov_b32 s9, s3
; GFX12-TRUE16-NEXT: s_mov_b32 s4, s0
; GFX12-TRUE16-NEXT: buffer_load_b32 v0, off, s[8:11], null
; GFX12-TRUE16-NEXT: s_mov_b32 s5, s1
; GFX12-TRUE16-NEXT: s_wait_loadcnt 0x0
; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v0
; GFX12-TRUE16-NEXT: v_sqrt_f16_e32 v0.l, v0.l
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(TRANS32_DEP_1)
; GFX12-TRUE16-NEXT: v_sqrt_f16_e32 v0.h, v1.l
; GFX12-TRUE16-NEXT: v_pack_b32_f16 v0, v0.l, v0.h
; GFX12-TRUE16-NEXT: buffer_store_b32 v0, off, s[4:7], null
; GFX12-TRUE16-NEXT: s_endpgm
;
; GFX12-FAKE16-LABEL: sqrt_v2f16:
; GFX12-FAKE16: ; %bb.0: ; %entry
; GFX12-FAKE16-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
; GFX12-FAKE16-NEXT: s_mov_b32 s6, -1
; GFX12-FAKE16-NEXT: s_mov_b32 s7, 0x31016000
; GFX12-FAKE16-NEXT: s_mov_b32 s10, s6
; GFX12-FAKE16-NEXT: s_mov_b32 s11, s7
; GFX12-FAKE16-NEXT: s_wait_kmcnt 0x0
; GFX12-FAKE16-NEXT: s_mov_b32 s8, s2
; GFX12-FAKE16-NEXT: s_mov_b32 s9, s3
; GFX12-FAKE16-NEXT: s_mov_b32 s4, s0
; GFX12-FAKE16-NEXT: buffer_load_b32 v0, off, s[8:11], null
; GFX12-FAKE16-NEXT: s_mov_b32 s5, s1
; GFX12-FAKE16-NEXT: s_wait_loadcnt 0x0
; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v1, 16, v0
; GFX12-FAKE16-NEXT: v_sqrt_f16_e32 v0, v0
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(TRANS32_DEP_1)
; GFX12-FAKE16-NEXT: v_sqrt_f16_e32 v1, v1
; GFX12-FAKE16-NEXT: v_pack_b32_f16 v0, v0, v1
; GFX12-FAKE16-NEXT: buffer_store_b32 v0, off, s[4:7], null
; GFX12-FAKE16-NEXT: s_endpgm
ptr addrspace(1) %r,
ptr addrspace(1) %a) {
entry:
Expand All @@ -197,5 +279,3 @@ entry:
store <2 x half> %r.val, ptr addrspace(1) %r
ret void
}
;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
; GFX11: {{.*}}
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