[Options] Add same-address constraint to the description of '-m[no]ld-seq-sa'

[Ami-zhang]

No description provided.

[llvmbot]

@llvm/pr-subscribers-backend-loongarch

@llvm/pr-subscribers-clang

Author: None (Ami-zhang)

Changes

---

Full diff: https://github.com/llvm/llvm-project/pull/141192.diff

2 Files Affected:

• (modified) clang/include/clang/Driver/Options.td (+2-2)
• (modified) llvm/lib/Target/LoongArch/LoongArch.td (+1-1)

diff --git a/clang/include/clang/Driver/Options.td b/clang/include/clang/Driver/Options.td
index 22261621df092..6226444af2d9a 100644
--- a/clang/include/clang/Driver/Options.td
+++ b/clang/include/clang/Driver/Options.td
@@ -5526,9 +5526,9 @@ def mlamcas : Flag<["-"], "mlamcas">, Group<m_loongarch_Features_Group>,
 def mno_lamcas : Flag<["-"], "mno-lamcas">, Group<m_loongarch_Features_Group>,
   HelpText<"Disable amcas[_db].{b/h/w/d}">;
 def mld_seq_sa : Flag<["-"], "mld-seq-sa">, Group<m_loongarch_Features_Group>,
-  HelpText<"Do not generate load-load barrier instructions (dbar 0x700)">;
+  HelpText<"Do not generate same-address load-load barrier instructions (dbar 0x700)">;
 def mno_ld_seq_sa : Flag<["-"], "mno-ld-seq-sa">, Group<m_loongarch_Features_Group>,
-  HelpText<"Generate load-load barrier instructions (dbar 0x700)">;
+  HelpText<"Generate same-address load-load barrier instructions (dbar 0x700)">;
 def mdiv32 : Flag<["-"], "mdiv32">, Group<m_loongarch_Features_Group>,
   HelpText<"Use div.w[u] and mod.w[u] instructions with input not sign-extended.">;
 def mno_div32 : Flag<["-"], "mno-div32">, Group<m_loongarch_Features_Group>,
diff --git a/llvm/lib/Target/LoongArch/LoongArch.td b/llvm/lib/Target/LoongArch/LoongArch.td
index 1d3dc3342a192..e1bb265be6673 100644
--- a/llvm/lib/Target/LoongArch/LoongArch.td
+++ b/llvm/lib/Target/LoongArch/LoongArch.td
@@ -135,7 +135,7 @@ def HasLAMCAS : Predicate<"Subtarget->hasLAMCAS()">;
 
 def FeatureLD_SEQ_SA
     : SubtargetFeature<"ld-seq-sa", "HasLD_SEQ_SA", "true",
-                        "Don't use load-load barrier (dbar 0x700).">;
+                        "Don't use a same-address load-load barrier (dbar 0x700).">;
 def HasLD_SEQ_SA : Predicate<"Subtarget->hasLD_SEQ_SA()">;
 
 // Assume div.w[u] and mod.w[u] can handle inputs that are not sign-extended.