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3 changes: 3 additions & 0 deletions llvm/lib/Target/RISCV/RISCVExpandPseudoInsts.cpp
Original file line number Diff line number Diff line change
Expand Up @@ -323,6 +323,8 @@ bool RISCVExpandPseudo::expandRV32ZdinxStore(MachineBasicBlock &MBB,
TRI->getSubReg(MBBI->getOperand(0).getReg(), RISCV::sub_gpr_even);
Register Hi =
TRI->getSubReg(MBBI->getOperand(0).getReg(), RISCV::sub_gpr_odd);
if (Hi == RISCV::DUMMY_REG_PAIR_WITH_X0)
Hi = RISCV::X0;

auto MIBLo = BuildMI(MBB, MBBI, DL, TII->get(RISCV::SW))
.addReg(Lo, getKillRegState(MBBI->getOperand(0).isKill()))
Expand Down Expand Up @@ -370,6 +372,7 @@ bool RISCVExpandPseudo::expandRV32ZdinxLoad(MachineBasicBlock &MBB,
TRI->getSubReg(MBBI->getOperand(0).getReg(), RISCV::sub_gpr_even);
Register Hi =
TRI->getSubReg(MBBI->getOperand(0).getReg(), RISCV::sub_gpr_odd);
assert(Hi != RISCV::DUMMY_REG_PAIR_WITH_X0 && "Cannot write to X0_Pair");

MachineInstrBuilder MIBLo, MIBHi;

Expand Down
13 changes: 9 additions & 4 deletions llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
Original file line number Diff line number Diff line change
Expand Up @@ -543,16 +543,21 @@ void RISCVInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
}

if (RISCV::GPRPairRegClass.contains(DstReg, SrcReg)) {
MCRegister EvenReg = TRI->getSubReg(SrcReg, RISCV::sub_gpr_even);
MCRegister OddReg = TRI->getSubReg(SrcReg, RISCV::sub_gpr_odd);
// We need to correct the odd register of X0_Pair.
if (OddReg == RISCV::DUMMY_REG_PAIR_WITH_X0)
OddReg == RISCV::X0;
assert(DstReg != RISCV::X0_Pair && "Cannot write to X0_Pair");

// Emit an ADDI for both parts of GPRPair.
BuildMI(MBB, MBBI, DL, get(RISCV::ADDI),
TRI->getSubReg(DstReg, RISCV::sub_gpr_even))
.addReg(TRI->getSubReg(SrcReg, RISCV::sub_gpr_even),
getKillRegState(KillSrc))
.addReg(EvenReg, getKillRegState(KillSrc))
.addImm(0);
BuildMI(MBB, MBBI, DL, get(RISCV::ADDI),
TRI->getSubReg(DstReg, RISCV::sub_gpr_odd))
.addReg(TRI->getSubReg(SrcReg, RISCV::sub_gpr_odd),
getKillRegState(KillSrc))
.addReg(OddReg, getKillRegState(KillSrc))
.addImm(0);
return;
}
Expand Down