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[MIPS] Reland Add FeatureMSA to i6400 and i6500 cores (#134985) #141730

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Merged
brad0 merged 2 commits into from
May 31, 2025
Merged

[MIPS] Reland Add FeatureMSA to i6400 and i6500 cores (#134985) #141730

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2bbd069
[MIPS] Reland Add FeatureMSA to i6400 and i6500 cores (#134985)
mgoudar May 7, 2025
d6d01e1
Initialize MipsSubtarget::ProcImpl to fix msan fail
mgoudar May 28, 2025
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6 changes: 6 additions & 0 deletions clang/lib/Driver/ToolChains/Arch/Mips.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -255,6 +255,12 @@ void mips::getMIPSTargetFeatures(const Driver &D, const llvm::Triple &Triple,
D.Diag(diag::err_drv_unsupported_noabicalls_pic);
}

if (CPUName == "i6500" || CPUName == "i6400") {
// MIPS cpu i6400 and i6500 support MSA (Mips SIMD Architecture)
// by default.
Features.push_back("+msa");
}

if (!UseAbiCalls)
Features.push_back("+noabicalls");
else
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9 changes: 9 additions & 0 deletions clang/test/Driver/mips-cpus.c
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@@ -0,0 +1,9 @@
// Check target CPUs are correctly passed.

// RUN: %clang --target=mips64 -### -c %s 2>&1 -mcpu=i6400 | FileCheck -check-prefix=MCPU-I6400 %s
// MCPU-I6400: "-target-cpu" "i6400"
// MCPU-I6400: "-target-feature" "+msa" "-target-feature" "-noabicalls"

// RUN: %clang --target=mips64 -### -c %s 2>&1 -mcpu=i6500 | FileCheck -check-prefix=MCPU-I6500 %s
// MCPU-I6500: "-target-cpu" "i6500"
// MCPU-I6500: "-target-feature" "+msa" "-target-feature" "-noabicalls"
4 changes: 2 additions & 2 deletions llvm/lib/Target/Mips/Mips.td
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Expand Up @@ -243,11 +243,11 @@ def ImplP5600 : SubtargetFeature<"p5600", "ProcImpl",
// same CPU architecture.
def ImplI6400
: SubtargetFeature<"i6400", "ProcImpl", "MipsSubtarget::CPU::I6400",
"MIPS I6400 Processor", [FeatureMips64r6]>;
"MIPS I6400 Processor", [FeatureMips64r6, FeatureMSA]>;

def ImplI6500
: SubtargetFeature<"i6500", "ProcImpl", "MipsSubtarget::CPU::I6500",
"MIPS I6500 Processor", [FeatureMips64r6]>;
"MIPS I6500 Processor", [FeatureMips64r6, FeatureMSA]>;

class Proc<string Name, list<SubtargetFeature> Features>
: ProcessorModel<Name, MipsGenericModel, Features>;
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7 changes: 3 additions & 4 deletions llvm/lib/Target/Mips/MipsSubtarget.h
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Expand Up @@ -43,7 +43,7 @@ class MipsSubtarget : public MipsGenSubtargetInfo {
Mips3, Mips4, Mips5, Mips64, Mips64r2, Mips64r3, Mips64r5, Mips64r6
};

enum class CPU { P5600, I6400, I6500 };
enum class CPU { Others, P5600, I6400, I6500 };

// Used to avoid printing dsp warnings multiple times.
static bool DspWarningPrinted;
Expand All @@ -66,9 +66,8 @@ class MipsSubtarget : public MipsGenSubtargetInfo {
// Mips architecture version
MipsArchEnum MipsArchVersion;

// Processor implementation (unused but required to exist by
// tablegen-erated code).
CPU ProcImpl;
// Processor implementation
CPU ProcImpl = CPU::Others;

// IsLittle - The target is Little Endian
bool IsLittle;
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2 changes: 2 additions & 0 deletions llvm/test/CodeGen/Mips/msa/arithmetic.ll
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@@ -1,6 +1,8 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=mips -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s --check-prefixes=ALL,MIPS
; RUN: llc -mtriple=mipsel -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s --check-prefixes=ALL,MIPSEL
; RUN: llc -mtriple=mips64 -mcpu=i6500 < %s | FileCheck %s --check-prefixes=ALL
; RUN: llc -mtriple=mips64 -mcpu=i6400 < %s | FileCheck %s --check-prefixes=ALL

define void @add_v16i8(ptr %c, ptr %a, ptr %b) nounwind {
; ALL-LABEL: add_v16i8:
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