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[AMDGPU] Handle direct loads to LDS in memory model #142018

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[AMDGPU] Handle direct loads to LDS in memory model #142018

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17 changes: 17 additions & 0 deletions llvm/lib/Target/AMDGPU/SIMemoryLegalizer.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -1084,6 +1084,7 @@ bool SIGfx6CacheControl::insertWait(MachineBasicBlock::iterator &MI,

bool VMCnt = false;
bool LGKMCnt = false;
bool DirectLDSWait = false;

if ((AddrSpace & (SIAtomicAddrSpace::GLOBAL | SIAtomicAddrSpace::SCRATCH)) !=
SIAtomicAddrSpace::NONE) {
Expand All @@ -1104,6 +1105,10 @@ bool SIGfx6CacheControl::insertWait(MachineBasicBlock::iterator &MI,
}

if ((AddrSpace & SIAtomicAddrSpace::LDS) != SIAtomicAddrSpace::NONE) {
// Wait for direct loads to LDS from global memory to ensure that
// LDS operations cannot be reordered with respect to global memory
// operations.
DirectLDSWait = true;
switch (Scope) {
case SIAtomicScope::SYSTEM:
case SIAtomicScope::AGENT:
Expand Down Expand Up @@ -1149,6 +1154,18 @@ bool SIGfx6CacheControl::insertWait(MachineBasicBlock::iterator &MI,
}
}

// Conservatively wait for vmcnt(0) to ensure that LDS operations and direct
// LDS loads from global memory cannot be reordered with respect to each
// other. This waitcnt can be safely optimized to wait for a higher vmcnt
// based on the number of outstanding direct LDS loads.
if (DirectLDSWait) {
unsigned WaitCntImmediate = AMDGPU::encodeWaitcnt(
IV, 0, getExpcntBitMask(IV), getLgkmcntBitMask(IV));
BuildMI(MBB, MI, DL, TII->get(AMDGPU::S_WAITCNT_DIRECT_LDS_LOAD_soft))
.addImm(WaitCntImmediate);
Changed = true;
}

if (VMCnt || LGKMCnt) {
unsigned WaitCntImmediate =
AMDGPU::encodeWaitcnt(IV,
Expand Down
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