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[AMDGPU] New RegBankSelect: Handle all 32/64 bit pointer types for B32/B64 rule #142560

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Merged
Pierre-vh merged 2 commits into from
Jun 19, 2025
Merged

[AMDGPU] New RegBankSelect: Handle all 32/64 bit pointer types for B32/B64 rule #142560

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9c08e37
[AMDGPU] New RegBankSelect: Map P0 to B64
Pierre-vh Jun 3, 2025
ac8e7d3
generalize changes
Pierre-vh Jun 3, 2025
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8 changes: 3 additions & 5 deletions llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -199,13 +199,11 @@ UniformityLLTOpPredicateID LLTToId(LLT Ty) {

UniformityLLTOpPredicateID LLTToBId(LLT Ty) {
if (Ty == LLT::scalar(32) || Ty == LLT::fixed_vector(2, 16) ||
Ty == LLT::pointer(3, 32) || Ty == LLT::pointer(5, 32) ||
Ty == LLT::pointer(6, 32))
(Ty.isPointer() && Ty.getSizeInBits() == 32))
return B32;
if (Ty == LLT::scalar(64) || Ty == LLT::fixed_vector(2, 32) ||
Ty == LLT::fixed_vector(4, 16) || Ty == LLT::pointer(1, 64) ||
Ty == LLT::pointer(4, 64) ||
(Ty.isPointer() && Ty.getAddressSpace() > AMDGPUAS::MAX_AMDGPU_ADDRESS))
Ty == LLT::fixed_vector(4, 16) ||
(Ty.isPointer() && Ty.getSizeInBits() == 64))
return B64;
if (Ty == LLT::fixed_vector(3, 32))
return B96;
Expand Down
196 changes: 196 additions & 0 deletions llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-select.mir
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Original file line number Diff line number Diff line change
Expand Up @@ -896,6 +896,31 @@ body: |
%5:_(<4 x s16>) = G_SELECT %4, %2, %3
...

---
name: select_p0_scc_ss
legalized: true
body: |
bb.0:
liveins: $sgpr0, $sgpr1, $sgpr2_sgpr3, $sgpr4_sgpr5
; CHECK-LABEL: name: select_p0_scc_ss
; CHECK: liveins: $sgpr0, $sgpr1, $sgpr2_sgpr3, $sgpr4_sgpr5
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
; CHECK-NEXT: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
; CHECK-NEXT: [[COPY2:%[0-9]+]]:sgpr(p0) = COPY $sgpr2_sgpr3
; CHECK-NEXT: [[COPY3:%[0-9]+]]:sgpr(p0) = COPY $sgpr4_sgpr5
; CHECK-NEXT: [[ICMP:%[0-9]+]]:sgpr(s32) = G_ICMP intpred(ne), [[COPY]](s32), [[COPY1]]
; CHECK-NEXT: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 1
; CHECK-NEXT: [[AND:%[0-9]+]]:sgpr(s32) = G_AND [[ICMP]], [[C]]
; CHECK-NEXT: [[SELECT:%[0-9]+]]:sgpr(p0) = G_SELECT [[AND]](s32), [[COPY2]], [[COPY3]]
%0:_(s32) = COPY $sgpr0
%1:_(s32) = COPY $sgpr1
%2:_(p0) = COPY $sgpr2_sgpr3
%3:_(p0) = COPY $sgpr4_sgpr5
%4:_(s1) = G_ICMP intpred(ne), %0, %1
%5:_(p0) = G_SELECT %4, %2, %3
...

---
name: select_p1_scc_ss
legalized: true
Expand Down Expand Up @@ -946,6 +971,36 @@ body: |
%5:_(p999) = G_SELECT %4, %2, %3
...

---
name: select_p0_scc_sv
legalized: true
body: |
bb.0:
liveins: $sgpr0, $sgpr1, $sgpr2_sgpr3, $vgpr0_vgpr1
; CHECK-LABEL: name: select_p0_scc_sv
; CHECK: liveins: $sgpr0, $sgpr1, $sgpr2_sgpr3, $vgpr0_vgpr1
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
; CHECK-NEXT: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
; CHECK-NEXT: [[COPY2:%[0-9]+]]:sgpr(p0) = COPY $sgpr2_sgpr3
; CHECK-NEXT: [[COPY3:%[0-9]+]]:vgpr(p0) = COPY $vgpr0_vgpr1
; CHECK-NEXT: [[ICMP:%[0-9]+]]:sgpr(s32) = G_ICMP intpred(ne), [[COPY]](s32), [[COPY1]]
; CHECK-NEXT: [[AMDGPU_COPY_VCC_SCC:%[0-9]+]]:vcc(s1) = G_AMDGPU_COPY_VCC_SCC [[ICMP]](s32)
; CHECK-NEXT: [[COPY4:%[0-9]+]]:vgpr(p0) = COPY [[COPY2]](p0)
; CHECK-NEXT: [[UV:%[0-9]+]]:vgpr(s32), [[UV1:%[0-9]+]]:vgpr(s32) = G_UNMERGE_VALUES [[COPY4]](p0)
; CHECK-NEXT: [[UV2:%[0-9]+]]:vgpr(s32), [[UV3:%[0-9]+]]:vgpr(s32) = G_UNMERGE_VALUES [[COPY3]](p0)
; CHECK-NEXT: [[SELECT:%[0-9]+]]:vgpr(s32) = G_SELECT [[AMDGPU_COPY_VCC_SCC]](s1), [[UV]], [[UV2]]
; CHECK-NEXT: [[SELECT1:%[0-9]+]]:vgpr(s32) = G_SELECT [[AMDGPU_COPY_VCC_SCC]](s1), [[UV1]], [[UV3]]
; CHECK-NEXT: [[MV:%[0-9]+]]:vgpr(p0) = G_MERGE_VALUES [[SELECT]](s32), [[SELECT1]](s32)
%0:_(s32) = COPY $sgpr0
%1:_(s32) = COPY $sgpr1
%2:_(p0) = COPY $sgpr2_sgpr3
%3:_(p0) = COPY $vgpr0_vgpr1
%4:_(s1) = G_ICMP intpred(ne), %0, %1
%5:_(p0) = G_SELECT %4, %2, %3

...

---
name: select_p1_scc_sv
legalized: true
Expand Down Expand Up @@ -976,6 +1031,35 @@ body: |

...

---
name: select_p0_scc_vs
legalized: true
body: |
bb.0:
liveins: $sgpr0, $sgpr1, $sgpr2_sgpr3, $vgpr0_vgpr1
; CHECK-LABEL: name: select_p0_scc_vs
; CHECK: liveins: $sgpr0, $sgpr1, $sgpr2_sgpr3, $vgpr0_vgpr1
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
; CHECK-NEXT: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
; CHECK-NEXT: [[COPY2:%[0-9]+]]:sgpr(p0) = COPY $sgpr2_sgpr3
; CHECK-NEXT: [[COPY3:%[0-9]+]]:vgpr(p0) = COPY $vgpr0_vgpr1
; CHECK-NEXT: [[ICMP:%[0-9]+]]:sgpr(s32) = G_ICMP intpred(ne), [[COPY]](s32), [[COPY1]]
; CHECK-NEXT: [[AMDGPU_COPY_VCC_SCC:%[0-9]+]]:vcc(s1) = G_AMDGPU_COPY_VCC_SCC [[ICMP]](s32)
; CHECK-NEXT: [[COPY4:%[0-9]+]]:vgpr(p0) = COPY [[COPY2]](p0)
; CHECK-NEXT: [[UV:%[0-9]+]]:vgpr(s32), [[UV1:%[0-9]+]]:vgpr(s32) = G_UNMERGE_VALUES [[COPY3]](p0)
; CHECK-NEXT: [[UV2:%[0-9]+]]:vgpr(s32), [[UV3:%[0-9]+]]:vgpr(s32) = G_UNMERGE_VALUES [[COPY4]](p0)
; CHECK-NEXT: [[SELECT:%[0-9]+]]:vgpr(s32) = G_SELECT [[AMDGPU_COPY_VCC_SCC]](s1), [[UV]], [[UV2]]
; CHECK-NEXT: [[SELECT1:%[0-9]+]]:vgpr(s32) = G_SELECT [[AMDGPU_COPY_VCC_SCC]](s1), [[UV1]], [[UV3]]
; CHECK-NEXT: [[MV:%[0-9]+]]:vgpr(p0) = G_MERGE_VALUES [[SELECT]](s32), [[SELECT1]](s32)
%0:_(s32) = COPY $sgpr0
%1:_(s32) = COPY $sgpr1
%2:_(p0) = COPY $sgpr2_sgpr3
%3:_(p0) = COPY $vgpr0_vgpr1
%4:_(s1) = G_ICMP intpred(ne), %0, %1
%5:_(p0) = G_SELECT %4, %3, %2
...

---
name: select_p1_scc_vs
legalized: true
Expand Down Expand Up @@ -1033,6 +1117,35 @@ body: |
%5:_(p1) = G_SELECT %4, %2, %3
...

---
name: select_p0_vcc_ss
legalized: true
body: |
bb.0:
liveins: $sgpr0_sgpr1, $sgpr2_sgpr3, $vgpr0, $vgpr1
; CHECK-LABEL: name: select_p0_vcc_ss
; CHECK: liveins: $sgpr0_sgpr1, $sgpr2_sgpr3, $vgpr0, $vgpr1
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:sgpr(p0) = COPY $sgpr0_sgpr1
; CHECK-NEXT: [[COPY1:%[0-9]+]]:sgpr(p0) = COPY $sgpr2_sgpr3
; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
; CHECK-NEXT: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY $vgpr1
; CHECK-NEXT: [[ICMP:%[0-9]+]]:vcc(s1) = G_ICMP intpred(ne), [[COPY2]](s32), [[COPY3]]
; CHECK-NEXT: [[COPY4:%[0-9]+]]:vgpr(p0) = COPY [[COPY]](p0)
; CHECK-NEXT: [[COPY5:%[0-9]+]]:vgpr(p0) = COPY [[COPY1]](p0)
; CHECK-NEXT: [[UV:%[0-9]+]]:vgpr(s32), [[UV1:%[0-9]+]]:vgpr(s32) = G_UNMERGE_VALUES [[COPY4]](p0)
; CHECK-NEXT: [[UV2:%[0-9]+]]:vgpr(s32), [[UV3:%[0-9]+]]:vgpr(s32) = G_UNMERGE_VALUES [[COPY5]](p0)
; CHECK-NEXT: [[SELECT:%[0-9]+]]:vgpr(s32) = G_SELECT [[ICMP]](s1), [[UV]], [[UV2]]
; CHECK-NEXT: [[SELECT1:%[0-9]+]]:vgpr(s32) = G_SELECT [[ICMP]](s1), [[UV1]], [[UV3]]
; CHECK-NEXT: [[MV:%[0-9]+]]:vgpr(p0) = G_MERGE_VALUES [[SELECT]](s32), [[SELECT1]](s32)
%0:_(p0) = COPY $sgpr0_sgpr1
%1:_(p0) = COPY $sgpr2_sgpr3
%2:_(s32) = COPY $vgpr0
%3:_(s32) = COPY $vgpr1
%4:_(s1) = G_ICMP intpred(ne), %2, %3
%5:_(p0) = G_SELECT %4, %0, %1
...

---
name: select_p1_vcc_ss
legalized: true
Expand Down Expand Up @@ -1062,6 +1175,34 @@ body: |
%5:_(p1) = G_SELECT %4, %0, %1
...

---
name: select_p0_vcc_sv
legalized: true
body: |
bb.0:
liveins: $sgpr0_sgpr1, $vgpr0, $vgpr1, $vgpr2_vgpr3
; CHECK-LABEL: name: select_p0_vcc_sv
; CHECK: liveins: $sgpr0_sgpr1, $vgpr0, $vgpr1, $vgpr2_vgpr3
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:sgpr(p0) = COPY $sgpr0_sgpr1
; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY $vgpr1
; CHECK-NEXT: [[COPY3:%[0-9]+]]:vgpr(p0) = COPY $vgpr2_vgpr3
; CHECK-NEXT: [[ICMP:%[0-9]+]]:vcc(s1) = G_ICMP intpred(ne), [[COPY1]](s32), [[COPY2]]
; CHECK-NEXT: [[COPY4:%[0-9]+]]:vgpr(p0) = COPY [[COPY]](p0)
; CHECK-NEXT: [[UV:%[0-9]+]]:vgpr(s32), [[UV1:%[0-9]+]]:vgpr(s32) = G_UNMERGE_VALUES [[COPY4]](p0)
; CHECK-NEXT: [[UV2:%[0-9]+]]:vgpr(s32), [[UV3:%[0-9]+]]:vgpr(s32) = G_UNMERGE_VALUES [[COPY3]](p0)
; CHECK-NEXT: [[SELECT:%[0-9]+]]:vgpr(s32) = G_SELECT [[ICMP]](s1), [[UV]], [[UV2]]
; CHECK-NEXT: [[SELECT1:%[0-9]+]]:vgpr(s32) = G_SELECT [[ICMP]](s1), [[UV1]], [[UV3]]
; CHECK-NEXT: [[MV:%[0-9]+]]:vgpr(p0) = G_MERGE_VALUES [[SELECT]](s32), [[SELECT1]](s32)
%0:_(p0) = COPY $sgpr0_sgpr1
%1:_(s32) = COPY $vgpr0
%2:_(s32) = COPY $vgpr1
%3:_(p0) = COPY $vgpr2_vgpr3
%4:_(s1) = G_ICMP intpred(ne), %1, %2
%5:_(p0) = G_SELECT %4, %0, %3
...

---
name: select_p1_vcc_sv
legalized: true
Expand Down Expand Up @@ -1090,6 +1231,34 @@ body: |
%5:_(p1) = G_SELECT %4, %0, %3
...

---
name: select_p0_vcc_vs
legalized: true
body: |
bb.0:
liveins: $sgpr0_sgpr1, $vgpr0, $vgpr1, $vgpr2_vgpr3
; CHECK-LABEL: name: select_p0_vcc_vs
; CHECK: liveins: $sgpr0_sgpr1, $vgpr0, $vgpr1, $vgpr2_vgpr3
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:sgpr(p0) = COPY $sgpr0_sgpr1
; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY $vgpr1
; CHECK-NEXT: [[COPY3:%[0-9]+]]:vgpr(p0) = COPY $vgpr2_vgpr3
; CHECK-NEXT: [[ICMP:%[0-9]+]]:vcc(s1) = G_ICMP intpred(ne), [[COPY1]](s32), [[COPY2]]
; CHECK-NEXT: [[COPY4:%[0-9]+]]:vgpr(p0) = COPY [[COPY]](p0)
; CHECK-NEXT: [[UV:%[0-9]+]]:vgpr(s32), [[UV1:%[0-9]+]]:vgpr(s32) = G_UNMERGE_VALUES [[COPY3]](p0)
; CHECK-NEXT: [[UV2:%[0-9]+]]:vgpr(s32), [[UV3:%[0-9]+]]:vgpr(s32) = G_UNMERGE_VALUES [[COPY4]](p0)
; CHECK-NEXT: [[SELECT:%[0-9]+]]:vgpr(s32) = G_SELECT [[ICMP]](s1), [[UV]], [[UV2]]
; CHECK-NEXT: [[SELECT1:%[0-9]+]]:vgpr(s32) = G_SELECT [[ICMP]](s1), [[UV1]], [[UV3]]
; CHECK-NEXT: [[MV:%[0-9]+]]:vgpr(p0) = G_MERGE_VALUES [[SELECT]](s32), [[SELECT1]](s32)
%0:_(p0) = COPY $sgpr0_sgpr1
%1:_(s32) = COPY $vgpr0
%2:_(s32) = COPY $vgpr1
%3:_(p0) = COPY $vgpr2_vgpr3
%4:_(s1) = G_ICMP intpred(ne), %1, %2
%5:_(p0) = G_SELECT %4, %3, %0
...

---
name: select_p1_vcc_vs
legalized: true
Expand Down Expand Up @@ -1118,6 +1287,33 @@ body: |
%5:_(p1) = G_SELECT %4, %3, %0
...

---
name: select_p0_vcc_vv
legalized: true
body: |
bb.0:
liveins: $vgpr0, $vgpr1, $vgpr2_vgpr3, $vgpr4_vgpr5
; CHECK-LABEL: name: select_p0_vcc_vv
; CHECK: liveins: $vgpr0, $vgpr1, $vgpr2_vgpr3, $vgpr4_vgpr5
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr1
; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr(p0) = COPY $vgpr2_vgpr3
; CHECK-NEXT: [[COPY3:%[0-9]+]]:vgpr(p0) = COPY $vgpr4_vgpr5
; CHECK-NEXT: [[ICMP:%[0-9]+]]:vcc(s1) = G_ICMP intpred(ne), [[COPY]](s32), [[COPY1]]
; CHECK-NEXT: [[UV:%[0-9]+]]:vgpr(s32), [[UV1:%[0-9]+]]:vgpr(s32) = G_UNMERGE_VALUES [[COPY2]](p0)
; CHECK-NEXT: [[UV2:%[0-9]+]]:vgpr(s32), [[UV3:%[0-9]+]]:vgpr(s32) = G_UNMERGE_VALUES [[COPY3]](p0)
; CHECK-NEXT: [[SELECT:%[0-9]+]]:vgpr(s32) = G_SELECT [[ICMP]](s1), [[UV]], [[UV2]]
; CHECK-NEXT: [[SELECT1:%[0-9]+]]:vgpr(s32) = G_SELECT [[ICMP]](s1), [[UV1]], [[UV3]]
; CHECK-NEXT: [[MV:%[0-9]+]]:vgpr(p0) = G_MERGE_VALUES [[SELECT]](s32), [[SELECT1]](s32)
%0:_(s32) = COPY $vgpr0
%1:_(s32) = COPY $vgpr1
%2:_(p0) = COPY $vgpr2_vgpr3
%3:_(p0) = COPY $vgpr4_vgpr5
%4:_(s1) = G_ICMP intpred(ne), %0, %1
%5:_(p0) = G_SELECT %4, %2, %3
...

---
name: select_p1_vcc_vv
legalized: true
Expand Down
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