[AMDGPU] New RegBankSelect: Add missing S/VGPR pointer types #142600

Pierre-vh · 2025-06-03T13:12:11Z

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Pierre-vh · 2025-06-03T13:12:28Z

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[AMDGPU] New RegBankSelect: Add missing S/VGPR pointer types #142600 👈 (View in Graphite)
[AMDGPU] New RegBankSelect: Handle all 32/64 bit pointer types for B32/B64 rule #142560 : 1 other dependent PR (#142601 )
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llvmbot · 2025-06-03T13:14:37Z

@llvm/pr-subscribers-backend-amdgpu

Author: Pierre van Houtryve (Pierre-vh)

Changes

Full diff: https://github.com/llvm/llvm-project/pull/142600.diff

3 Files Affected:

(modified) llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeHelper.cpp (+31)
(modified) llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp (+18)
(modified) llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.h (+16)

diff --git a/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeHelper.cpp b/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeHelper.cpp
index 7ff822c6f6580..6b0fb9f925b82 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeHelper.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeHelper.cpp
@@ -557,10 +557,14 @@ LLT RegBankLegalizeHelper::getTyFromID(RegBankLLTMappingApplyID ID) {
   case Vgpr64:
     return LLT::scalar(64);
   case VgprP0:
+  case SgprP0:
     return LLT::pointer(0, 64);
   case SgprP1:
   case VgprP1:
     return LLT::pointer(1, 64);
+  case SgprP2:
+  case VgprP2:
+    return LLT::pointer(2, 32);
   case SgprP3:
   case VgprP3:
     return LLT::pointer(3, 32);
@@ -570,6 +574,12 @@ LLT RegBankLegalizeHelper::getTyFromID(RegBankLLTMappingApplyID ID) {
   case SgprP5:
   case VgprP5:
     return LLT::pointer(5, 32);
+  case SgprP6:
+  case VgprP6:
+    return LLT::pointer(6, 32);
+  case SgprP8:
+  case VgprP8:
+    return LLT::pointer(8, 128);
   case SgprV2S16:
   case VgprV2S16:
   case UniInVgprV2S16:
@@ -646,10 +656,14 @@ RegBankLegalizeHelper::getRegBankFromID(RegBankLLTMappingApplyID ID) {
   case Sgpr16:
   case Sgpr32:
   case Sgpr64:
+  case SgprP0:
   case SgprP1:
+  case SgprP2:
   case SgprP3:
   case SgprP4:
   case SgprP5:
+  case SgprP6:
+  case SgprP8:
   case SgprV2S16:
   case SgprV2S32:
   case SgprV4S32:
@@ -680,9 +694,12 @@ RegBankLegalizeHelper::getRegBankFromID(RegBankLLTMappingApplyID ID) {
   case Vgpr64:
   case VgprP0:
   case VgprP1:
+  case VgprP2:
   case VgprP3:
   case VgprP4:
   case VgprP5:
+  case VgprP6:
+  case VgprP8:
   case VgprV2S16:
   case VgprV2S32:
   case VgprV4S32:
@@ -718,10 +735,14 @@ void RegBankLegalizeHelper::applyMappingDst(
     case Sgpr16:
     case Sgpr32:
     case Sgpr64:
+    case SgprP0:
     case SgprP1:
+    case SgprP2:
     case SgprP3:
     case SgprP4:
     case SgprP5:
+    case SgprP6:
+    case SgprP8:
     case SgprV2S16:
     case SgprV2S32:
     case SgprV4S32:
@@ -730,9 +751,12 @@ void RegBankLegalizeHelper::applyMappingDst(
     case Vgpr64:
     case VgprP0:
     case VgprP1:
+    case VgprP2:
     case VgprP3:
     case VgprP4:
     case VgprP5:
+    case VgprP6:
+    case VgprP8:
     case VgprV2S16:
     case VgprV2S32:
     case VgprV4S32: {
@@ -839,10 +863,14 @@ void RegBankLegalizeHelper::applyMappingSrc(
     case Sgpr16:
     case Sgpr32:
     case Sgpr64:
+    case SgprP0:
     case SgprP1:
+    case SgprP2:
     case SgprP3:
     case SgprP4:
     case SgprP5:
+    case SgprP6:
+    case SgprP8:
     case SgprV2S16:
     case SgprV2S32:
     case SgprV4S32: {
@@ -867,9 +895,12 @@ void RegBankLegalizeHelper::applyMappingSrc(
     case Vgpr64:
     case VgprP0:
     case VgprP1:
+    case VgprP2:
     case VgprP3:
     case VgprP4:
     case VgprP5:
+    case VgprP6:
+    case VgprP8:
     case VgprV2S16:
     case VgprV2S32:
     case VgprV4S32: {
diff --git a/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp b/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp
index 5e21f44f7d545..d7ff1a9080b72 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp
@@ -54,12 +54,18 @@ bool matchUniformityAndLLT(Register Reg, UniformityLLTOpPredicateID UniID,
     return MRI.getType(Reg) == LLT::pointer(0, 64);
   case P1:
     return MRI.getType(Reg) == LLT::pointer(1, 64);
+  case P2:
+    return MRI.getType(Reg) == LLT::pointer(2, 32);
   case P3:
     return MRI.getType(Reg) == LLT::pointer(3, 32);
   case P4:
     return MRI.getType(Reg) == LLT::pointer(4, 64);
   case P5:
     return MRI.getType(Reg) == LLT::pointer(5, 32);
+  case P6:
+    return MRI.getType(Reg) == LLT::pointer(6, 32);
+  case P8:
+    return MRI.getType(Reg) == LLT::pointer(8, 128);
   case V2S32:
     return MRI.getType(Reg) == LLT::fixed_vector(2, 32);
   case V4S32:
@@ -88,12 +94,18 @@ bool matchUniformityAndLLT(Register Reg, UniformityLLTOpPredicateID UniID,
     return MRI.getType(Reg) == LLT::pointer(0, 64) && MUI.isUniform(Reg);
   case UniP1:
     return MRI.getType(Reg) == LLT::pointer(1, 64) && MUI.isUniform(Reg);
+  case UniP2:
+    return MRI.getType(Reg) == LLT::pointer(2, 32) && MUI.isUniform(Reg);
   case UniP3:
     return MRI.getType(Reg) == LLT::pointer(3, 32) && MUI.isUniform(Reg);
   case UniP4:
     return MRI.getType(Reg) == LLT::pointer(4, 64) && MUI.isUniform(Reg);
   case UniP5:
     return MRI.getType(Reg) == LLT::pointer(5, 32) && MUI.isUniform(Reg);
+  case UniP6:
+    return MRI.getType(Reg) == LLT::pointer(6, 32) && MUI.isUniform(Reg);
+  case UniP8:
+    return MRI.getType(Reg) == LLT::pointer(8, 128) && MUI.isUniform(Reg);
   case UniV2S16:
     return MRI.getType(Reg) == LLT::fixed_vector(2, 16) && MUI.isUniform(Reg);
   case UniB32:
@@ -120,12 +132,18 @@ bool matchUniformityAndLLT(Register Reg, UniformityLLTOpPredicateID UniID,
     return MRI.getType(Reg) == LLT::pointer(0, 64) && MUI.isDivergent(Reg);
   case DivP1:
     return MRI.getType(Reg) == LLT::pointer(1, 64) && MUI.isDivergent(Reg);
+  case DivP2:
+    return MRI.getType(Reg) == LLT::pointer(2, 32) && MUI.isDivergent(Reg);
   case DivP3:
     return MRI.getType(Reg) == LLT::pointer(3, 32) && MUI.isDivergent(Reg);
   case DivP4:
     return MRI.getType(Reg) == LLT::pointer(4, 64) && MUI.isDivergent(Reg);
   case DivP5:
     return MRI.getType(Reg) == LLT::pointer(5, 32) && MUI.isDivergent(Reg);
+  case DivP6:
+    return MRI.getType(Reg) == LLT::pointer(6, 32) && MUI.isDivergent(Reg);
+  case DivP8:
+    return MRI.getType(Reg) == LLT::pointer(8, 128) && MUI.isDivergent(Reg);
   case DivV2S16:
     return MRI.getType(Reg) == LLT::fixed_vector(2, 16) && MUI.isDivergent(Reg);
   case DivB32:
diff --git a/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.h b/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.h
index bddfb8dd1913f..a7a5b0ebba187 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.h
+++ b/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.h
@@ -53,21 +53,30 @@ enum UniformityLLTOpPredicateID {
   // pointers
   P0,
   P1,
+  P2,
   P3,
   P4,
   P5,
+  P6,
+  P8,
 
   UniP0,
   UniP1,
+  UniP2,
   UniP3,
   UniP4,
   UniP5,
+  UniP6,
+  UniP8,
 
   DivP0,
   DivP1,
+  DivP2,
   DivP3,
   DivP4,
   DivP5,
+  DivP6,
+  DivP8,
 
   // vectors
   V2S16,
@@ -117,10 +126,14 @@ enum RegBankLLTMappingApplyID {
   Sgpr16,
   Sgpr32,
   Sgpr64,
+  SgprP0,
   SgprP1,
+  SgprP2,
   SgprP3,
   SgprP4,
   SgprP5,
+  SgprP6,
+  SgprP8,
   SgprV2S16,
   SgprV4S32,
   SgprV2S32,
@@ -137,9 +150,12 @@ enum RegBankLLTMappingApplyID {
   Vgpr64,
   VgprP0,
   VgprP1,
+  VgprP2,
   VgprP3,
   VgprP4,
   VgprP5,
+  VgprP6,
+  VgprP8,
   VgprV2S16,
   VgprV2S32,
   VgprB32,

jayfoad

Do we really need all this duplication? I am not looking forward to adding support for a new address space :(

tgymnich · 2025-06-03T14:00:24Z

maybe add tests?

arsenm

We shouldn't need to treat every address space as unique, just 32 or 64 bit

petar-avramovic · 2025-06-03T14:22:43Z

Don't like adding all these without use case.
Not sure if we can get away with only checking ptr size and ignoring address space but in the end it is mostly used for assert.
These are mostly used for loads/stores and atomics, is it really that simple, all 32bit pointer types should have same rules?

arsenm · 2025-06-03T14:37:27Z

These are mostly used for loads/stores and atomics, is it really that simple, all 32bit pointer types should have same rules?

Yes

[AMDGPU] New RegBankSelect: Add missing S/VGPR pointer types

2665b0c

Pierre-vh requested review from arsenm, jayfoad, petar-avramovic and tgymnich and removed request for tgymnich June 3, 2025 13:13

Pierre-vh marked this pull request as ready for review June 3, 2025 13:14

llvmbot added the backend:AMDGPU label Jun 3, 2025

jayfoad reviewed Jun 3, 2025

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tgymnich approved these changes Jun 3, 2025

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arsenm reviewed Jun 3, 2025

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Pierre-vh closed this Jun 4, 2025

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