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[AMDGPU] New RegBanKSelect: Add S128 types #142601

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Merged
Pierre-vh merged 1 commit into from
Jun 19, 2025
Merged

[AMDGPU] New RegBanKSelect: Add S128 types #142601

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9 changes: 9 additions & 0 deletions llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeHelper.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -556,6 +556,9 @@ LLT RegBankLegalizeHelper::getTyFromID(RegBankLLTMappingApplyID ID) {
case Sgpr64:
case Vgpr64:
return LLT::scalar(64);
case Sgpr128:
case Vgpr128:
return LLT::scalar(128);
case VgprP0:
return LLT::pointer(0, 64);
case SgprP1:
Expand Down Expand Up @@ -646,6 +649,7 @@ RegBankLegalizeHelper::getRegBankFromID(RegBankLLTMappingApplyID ID) {
case Sgpr16:
case Sgpr32:
case Sgpr64:
case Sgpr128:
case SgprP1:
case SgprP3:
case SgprP4:
Expand Down Expand Up @@ -678,6 +682,7 @@ RegBankLegalizeHelper::getRegBankFromID(RegBankLLTMappingApplyID ID) {
case Vgpr16:
case Vgpr32:
case Vgpr64:
case Vgpr128:
case VgprP0:
case VgprP1:
case VgprP3:
Expand Down Expand Up @@ -718,6 +723,7 @@ void RegBankLegalizeHelper::applyMappingDst(
case Sgpr16:
case Sgpr32:
case Sgpr64:
case Sgpr128:
case SgprP1:
case SgprP3:
case SgprP4:
Expand All @@ -728,6 +734,7 @@ void RegBankLegalizeHelper::applyMappingDst(
case Vgpr16:
case Vgpr32:
case Vgpr64:
case Vgpr128:
case VgprP0:
case VgprP1:
case VgprP3:
Expand Down Expand Up @@ -839,6 +846,7 @@ void RegBankLegalizeHelper::applyMappingSrc(
case Sgpr16:
case Sgpr32:
case Sgpr64:
case Sgpr128:
case SgprP1:
case SgprP3:
case SgprP4:
Expand All @@ -865,6 +873,7 @@ void RegBankLegalizeHelper::applyMappingSrc(
case Vgpr16:
case Vgpr32:
case Vgpr64:
case Vgpr128:
case VgprP0:
case VgprP1:
case VgprP3:
Expand Down
6 changes: 6 additions & 0 deletions llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -50,6 +50,8 @@ bool matchUniformityAndLLT(Register Reg, UniformityLLTOpPredicateID UniID,
return MRI.getType(Reg) == LLT::scalar(32);
case S64:
return MRI.getType(Reg) == LLT::scalar(64);
case S128:
return MRI.getType(Reg) == LLT::scalar(128);
case P0:
return MRI.getType(Reg) == LLT::pointer(0, 64);
case P1:
Expand Down Expand Up @@ -84,6 +86,8 @@ bool matchUniformityAndLLT(Register Reg, UniformityLLTOpPredicateID UniID,
return MRI.getType(Reg) == LLT::scalar(32) && MUI.isUniform(Reg);
case UniS64:
return MRI.getType(Reg) == LLT::scalar(64) && MUI.isUniform(Reg);
case UniS128:
return MRI.getType(Reg) == LLT::scalar(128) && MUI.isUniform(Reg);
case UniP0:
return MRI.getType(Reg) == LLT::pointer(0, 64) && MUI.isUniform(Reg);
case UniP1:
Expand Down Expand Up @@ -116,6 +120,8 @@ bool matchUniformityAndLLT(Register Reg, UniformityLLTOpPredicateID UniID,
return MRI.getType(Reg) == LLT::scalar(32) && MUI.isDivergent(Reg);
case DivS64:
return MRI.getType(Reg) == LLT::scalar(64) && MUI.isDivergent(Reg);
case DivS128:
return MRI.getType(Reg) == LLT::scalar(128) && MUI.isDivergent(Reg);
case DivP0:
return MRI.getType(Reg) == LLT::pointer(0, 64) && MUI.isDivergent(Reg);
case DivP1:
Expand Down
5 changes: 5 additions & 0 deletions llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.h
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Original file line number Diff line number Diff line change
Expand Up @@ -39,16 +39,19 @@ enum UniformityLLTOpPredicateID {
S16,
S32,
S64,
S128,

UniS1,
UniS16,
UniS32,
UniS64,
UniS128,

DivS1,
DivS16,
DivS32,
DivS64,
DivS128,

// pointers
P0,
Expand Down Expand Up @@ -117,6 +120,7 @@ enum RegBankLLTMappingApplyID {
Sgpr16,
Sgpr32,
Sgpr64,
Sgpr128,
SgprP1,
SgprP3,
SgprP4,
Expand All @@ -135,6 +139,7 @@ enum RegBankLLTMappingApplyID {
Vgpr16,
Vgpr32,
Vgpr64,
Vgpr128,
VgprP0,
VgprP1,
VgprP3,
Expand Down
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