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[HLSL] Use ExtVector for firstbit intrinsics #142679

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Merged
merged 2 commits into from
Jun 17, 2025
Merged

[HLSL] Use ExtVector for firstbit intrinsics #142679

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[HLSL] Use ExtVector for firstbit intrinsics
V-FEXrt Jun 3, 2025
9ba8e0f
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V-FEXrt Jun 4, 2025
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8 changes: 4 additions & 4 deletions clang/lib/Sema/SemaHLSL.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -2171,8 +2171,9 @@ static void SetElementTypeAsReturnType(Sema *S, CallExpr *TheCall,
QualType ReturnType) {
auto *VecTyA = TheCall->getArg(0)->getType()->getAs<VectorType>();
if (VecTyA)
ReturnType = S->Context.getVectorType(ReturnType, VecTyA->getNumElements(),
VectorKind::Generic);
ReturnType =
S->Context.getExtVectorType(ReturnType, VecTyA->getNumElements());

TheCall->setType(ReturnType);
}

Expand Down Expand Up @@ -2485,8 +2486,7 @@ bool SemaHLSL::CheckBuiltinFunctionCall(unsigned BuiltinID, CallExpr *TheCall) {

if (auto *VecTy = EltTy->getAs<VectorType>()) {
EltTy = VecTy->getElementType();
ResTy = SemaRef.Context.getVectorType(ResTy, VecTy->getNumElements(),
VecTy->getVectorKind());
ResTy = SemaRef.Context.getExtVectorType(ResTy, VecTy->getNumElements());
}

if (!EltTy->isIntegerType()) {
Expand Down
8 changes: 8 additions & 0 deletions clang/test/CodeGenHLSL/builtins/firstbithigh.hlsl
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Expand Up @@ -151,3 +151,11 @@ uint3 test_firstbithigh_long3(int64_t3 p0) {
uint4 test_firstbithigh_long4(int64_t4 p0) {
return firstbithigh(p0);
}

// CHECK-LABEL: test_firstbithigh_upcast
// CHECK: [[FBH:%.*]] = call <4 x i32> @llvm.[[TARGET]].firstbituhigh.v4i32(<4 x i32> %{{.*}})
// CHECK: [[CONV:%.*]] = zext <4 x i32> [[FBH]] to <4 x i64>
// CHECK: ret <4 x i64> [[CONV]]
uint64_t4 test_firstbithigh_upcast(uint4 p0) {
return firstbithigh(p0);
}
8 changes: 8 additions & 0 deletions clang/test/CodeGenHLSL/builtins/firstbitlow.hlsl
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Expand Up @@ -151,3 +151,11 @@ uint3 test_firstbitlow_long3(int64_t3 p0) {
uint4 test_firstbitlow_long4(int64_t4 p0) {
return firstbitlow(p0);
}

// CHECK-LABEL: test_firstbitlow_upcast
// CHECK: [[FBL:%.*]] = call <4 x i32> @llvm.[[TARGET]].firstbitlow.v4i32(<4 x i32> %{{.*}})
// CHECK: [[CONV:%.*]] = zext <4 x i32> [[FBL]] to <4 x i64>
// CHECK: ret <4 x i64> [[CONV]]
uint64_t4 test_firstbitlow_upcast(uint4 p0) {
return firstbitlow(p0);
}