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[RISCV] Guard the alternative static chain register use on ILP32E/LP64E #142715

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Merged
merged 7 commits into from
Jun 11, 2025
Merged

[RISCV] Guard the alternative static chain register use on ILP32E/LP64E #142715

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2086670
[RISCV] Guard the alternative static chain register use on RV32E
jaidTw Jun 4, 2025
8e410de
Addressed comments
jaidTw Jun 4, 2025
01b7986
Update llvm/lib/Target/RISCV/RISCVCallingConv.cpp
jaidTw Jun 4, 2025
ac506b1
clang-format
jaidTw Jun 4, 2025
db6d7b1
Update llvm/lib/Target/RISCV/RISCVCallingConv.cpp
jaidTw Jun 11, 2025
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Add test
jaidTw Jun 11, 2025
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clang-format
jaidTw Jun 11, 2025
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24 changes: 16 additions & 8 deletions llvm/lib/Target/RISCV/RISCVCallingConv.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -333,15 +333,23 @@ bool llvm::CC_RISCV(unsigned ValNo, MVT ValVT, MVT LocVT,
unsigned XLen = Subtarget.getXLen();
MVT XLenVT = Subtarget.getXLenVT();

// Static chain parameter must not be passed in normal argument registers,
// so we assign t2/t3 for it as done in GCC's __builtin_call_with_static_chain
bool HasCFBranch =
Subtarget.hasStdExtZicfilp() &&
MF.getFunction().getParent()->getModuleFlag("cf-protection-branch");
// Normal: t2, Branch control flow protection: t3
const auto StaticChainReg = HasCFBranch ? RISCV::X28 : RISCV::X7;

if (ArgFlags.isNest()) {
// Static chain parameter must not be passed in normal argument registers,
// so we assign t2/t3 for it as done in GCC's
// __builtin_call_with_static_chain
bool HasCFBranch =
Subtarget.hasStdExtZicfilp() &&
MF.getFunction().getParent()->getModuleFlag("cf-protection-branch");

// Normal: t2, Branch control flow protection: t3
const auto StaticChainReg = HasCFBranch ? RISCV::X28 : RISCV::X7;

RISCVABI::ABI ABI = Subtarget.getTargetABI();
if (HasCFBranch &&
(ABI == RISCVABI::ABI_ILP32E || ABI == RISCVABI::ABI_LP64E))
reportFatalUsageError(
"Nested functions with control flow protection are not "
"usable with ILP32E or LP64E ABI.");
if (MCRegister Reg = State.AllocateReg(StaticChainReg)) {
State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
return false;
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3 changes: 3 additions & 0 deletions llvm/test/CodeGen/RISCV/nest-register.ll
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Expand Up @@ -5,6 +5,8 @@
; RUN: | FileCheck -check-prefix=RV64I %s
; RUN: llc -mtriple=riscv64 -mattr=+experimental-zicfilp -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefix=RV64I-ZICFILP %s
; RUN: not llc -mtriple=riscv64 -target-abi=lp64e -mattr=+experimental-zicfilp \
; RUN: -verify-machineinstrs < %s 2>&1 | FileCheck -check-prefix=LP64E-ZICFILP %s

; Tests that the 'nest' parameter attribute causes the relevant parameter to be
; passed in the right register.
Expand Down Expand Up @@ -63,6 +65,7 @@ define ptr @nest_caller(ptr %arg) nounwind {
ret ptr %result
}

; LP64E-ZICFILP: LLVM ERROR: Nested functions with control flow protection are not usable with ILP32E or LP64E ABI.
!llvm.module.flags = !{!0}

!0 = !{i32 8, !"cf-protection-branch", i32 1}
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