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[RISCV] Guard the alternative static chain register use on ILP32E/LP64E #142715

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Merged
merged 7 commits into from
Jun 11, 2025
Merged

[RISCV] Guard the alternative static chain register use on ILP32E/LP64E #142715

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2086670
[RISCV] Guard the alternative static chain register use on RV32E
jaidTw Jun 4, 2025
8e410de
Addressed comments
jaidTw Jun 4, 2025
01b7986
Update llvm/lib/Target/RISCV/RISCVCallingConv.cpp
jaidTw Jun 4, 2025
ac506b1
clang-format
jaidTw Jun 4, 2025
db6d7b1
Update llvm/lib/Target/RISCV/RISCVCallingConv.cpp
jaidTw Jun 11, 2025
d1a7d52
Add test
jaidTw Jun 11, 2025
18a662a
clang-format
jaidTw Jun 11, 2025
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4 changes: 4 additions & 0 deletions llvm/lib/Target/RISCV/RISCVCallingConv.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -338,6 +338,10 @@ bool llvm::CC_RISCV(unsigned ValNo, MVT ValVT, MVT LocVT,
bool HasCFBranch =
Subtarget.hasStdExtZicfilp() &&
MF.getFunction().getParent()->getModuleFlag("cf-protection-branch");
if (HasCFBranch && (Subtarget.isRV32() && Subtarget.hasStdExtE()))
reportFatalUsageError(
"Alternative static chain register is not supported on RV32E");

// Normal: t2, Branch control flow protection: t3
const auto StaticChainReg = HasCFBranch ? RISCV::X28 : RISCV::X7;

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