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[RISCV] Select unsigned bitfield insert for XAndesPerf #142737

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Merged
tclin914 merged 4 commits into from
Jun 6, 2025
Merged

[RISCV] Select unsigned bitfield insert for XAndesPerf #142737

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4d5c0f4
[RISCV] Pre-commit
tclin914 Jun 3, 2025
27d670f
[RISCV] Select unsigned bitfield insert for XAndesPerf
tclin914 Jun 3, 2025
de9c8ce
Make the lsb/msb arguments/variables to truly be least significant bit
tclin914 Jun 5, 2025
1c38d74
Move the selection of 0 into `tryUnsignedBitfieldInsertInZero`
tclin914 Jun 5, 2025
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15 changes: 6 additions & 9 deletions llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -699,8 +699,8 @@ bool RISCVDAGToDAGISel::tryUnsignedBitfieldInsertInZero(SDNode *Node, SDLoc DL,
unsigned Opc = RISCV::NDS_BFOZ;

SDNode *Ubi = CurDAG->getMachineNode(Opc, DL, VT, X,
CurDAG->getTargetConstant(Msb, DL, VT),
CurDAG->getTargetConstant(Lsb, DL, VT));
CurDAG->getTargetConstant(Lsb, DL, VT),
CurDAG->getTargetConstant(Msb, DL, VT));
ReplaceNode(Node, Ubi);
return true;
}
Expand Down Expand Up @@ -1348,13 +1348,10 @@ void RISCVDAGToDAGISel::Select(SDNode *Node) {
// e.g.
// (and (shl x, 12), 0x00fff000)
// If XLen = 32 and C2 = 12, then
// Len = 32 - 8 - 12 = 12,
// Lsb = 32 - 8 - 1 = 23 and Msb = 12
// -> nds.bfoz x, 12, 23
const unsigned Len = XLen - Leading - C2;
const unsigned Lsb = XLen - Leading - 1;
// If Len is 1, the Msb will be 0 instead of C2.
unsigned Msb = Len == 1 ? 0 : C2;
// Msb = 32 - 8 - 1 = 23 and Lsb = 12
const unsigned Msb = XLen - Leading - 1;
// If Msb is equal to C2, the Lsb will be 0 instead of C2.
unsigned Lsb = Msb == C2 ? 0 : C2;
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@topperc topperc Jun 5, 2025

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Can we set Lsb = C2 here and move the selection of 0 into tryUnsignedBitfieldInsertInZero. This behavior may specific to Andes.

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@tclin914 tclin914 Jun 5, 2025

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Done. Thanks.

if (tryUnsignedBitfieldInsertInZero(Node, DL, VT, X, Msb, Lsb))
return;

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