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[AArch64][InstCombine] Combine AES instructions with zero operands. #142781

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Merged
merged 3 commits into from
Jun 9, 2025
Merged

[AArch64][InstCombine] Combine AES instructions with zero operands. #142781

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618c6f2
Precommit tests.
rj-jesus Jun 4, 2025
2c3d0d8
[AArch64][InstCombine] Combine AES instructions with zero operands.
rj-jesus Jun 4, 2025
8ffefea
Add SVE zero RHS tests.
rj-jesus Jun 5, 2025
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8 changes: 7 additions & 1 deletion llvm/lib/Transforms/InstCombine/InstCombineCalls.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -3076,10 +3076,16 @@ Instruction *InstCombinerImpl::visitCallInst(CallInst &CI) {
case Intrinsic::arm_neon_aesd:
case Intrinsic::arm_neon_aese:
case Intrinsic::aarch64_crypto_aesd:
case Intrinsic::aarch64_crypto_aese: {
case Intrinsic::aarch64_crypto_aese:
case Intrinsic::aarch64_sve_aesd:
case Intrinsic::aarch64_sve_aese: {
Value *DataArg = II->getArgOperand(0);
Value *KeyArg = II->getArgOperand(1);

// Accept zero on either operand.
if (!match(KeyArg, m_ZeroInt()))
std::swap(KeyArg, DataArg);

// Try to use the builtin XOR in AESE and AESD to eliminate a prior XOR
Value *Data, *Key;
if (match(KeyArg, m_ZeroInt()) &&
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48 changes: 48 additions & 0 deletions llvm/test/Transforms/InstCombine/AArch64/aes-intrinsics.ll
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Original file line number Diff line number Diff line change
Expand Up @@ -13,6 +13,17 @@ define <16 x i8> @combineXorAeseZeroARM64(<16 x i8> %data, <16 x i8> %key) {
ret <16 x i8> %data.aes
}

define <16 x i8> @combineXorAeseZeroLhsARM64(<16 x i8> %data, <16 x i8> %key) {
; CHECK-LABEL: define <16 x i8> @combineXorAeseZeroLhsARM64(
; CHECK-SAME: <16 x i8> [[DATA:%.*]], <16 x i8> [[KEY:%.*]]) {
; CHECK-NEXT: [[DATA_AES:%.*]] = tail call <16 x i8> @llvm.aarch64.crypto.aese(<16 x i8> [[DATA]], <16 x i8> [[KEY]])
; CHECK-NEXT: ret <16 x i8> [[DATA_AES]]
;
%data.xor = xor <16 x i8> %data, %key
%data.aes = tail call <16 x i8> @llvm.aarch64.crypto.aese(<16 x i8> zeroinitializer, <16 x i8> %data.xor)
ret <16 x i8> %data.aes
}

define <16 x i8> @combineXorAeseNonZeroARM64(<16 x i8> %data, <16 x i8> %key) {
; CHECK-LABEL: define <16 x i8> @combineXorAeseNonZeroARM64(
; CHECK-SAME: <16 x i8> [[DATA:%.*]], <16 x i8> [[KEY:%.*]]) {
Expand All @@ -36,6 +47,17 @@ define <16 x i8> @combineXorAesdZeroARM64(<16 x i8> %data, <16 x i8> %key) {
ret <16 x i8> %data.aes
}

define <16 x i8> @combineXorAesdZeroLhsARM64(<16 x i8> %data, <16 x i8> %key) {
; CHECK-LABEL: define <16 x i8> @combineXorAesdZeroLhsARM64(
; CHECK-SAME: <16 x i8> [[DATA:%.*]], <16 x i8> [[KEY:%.*]]) {
; CHECK-NEXT: [[DATA_AES:%.*]] = tail call <16 x i8> @llvm.aarch64.crypto.aesd(<16 x i8> [[DATA]], <16 x i8> [[KEY]])
; CHECK-NEXT: ret <16 x i8> [[DATA_AES]]
;
%data.xor = xor <16 x i8> %data, %key
%data.aes = tail call <16 x i8> @llvm.aarch64.crypto.aesd(<16 x i8> zeroinitializer, <16 x i8> %data.xor)
ret <16 x i8> %data.aes
}

define <16 x i8> @combineXorAesdNonZeroARM64(<16 x i8> %data, <16 x i8> %key) {
; CHECK-LABEL: define <16 x i8> @combineXorAesdNonZeroARM64(
; CHECK-SAME: <16 x i8> [[DATA:%.*]], <16 x i8> [[KEY:%.*]]) {
Expand All @@ -51,3 +73,29 @@ define <16 x i8> @combineXorAesdNonZeroARM64(<16 x i8> %data, <16 x i8> %key) {
declare <16 x i8> @llvm.aarch64.crypto.aese(<16 x i8>, <16 x i8>) #0
declare <16 x i8> @llvm.aarch64.crypto.aesd(<16 x i8>, <16 x i8>) #0

; SVE

define <vscale x 16 x i8> @combineXorAeseZeroSVE(<vscale x 16 x i8> %data, <vscale x 16 x i8> %key) {
; CHECK-LABEL: define <vscale x 16 x i8> @combineXorAeseZeroSVE(
; CHECK-SAME: <vscale x 16 x i8> [[DATA:%.*]], <vscale x 16 x i8> [[KEY:%.*]]) {
; CHECK-NEXT: [[DATA_AES:%.*]] = tail call <vscale x 16 x i8> @llvm.aarch64.sve.aese(<vscale x 16 x i8> [[DATA]], <vscale x 16 x i8> [[KEY]])
; CHECK-NEXT: ret <vscale x 16 x i8> [[DATA_AES]]
;
%data.xor = xor <vscale x 16 x i8> %data, %key
%data.aes = tail call <vscale x 16 x i8> @llvm.aarch64.sve.aese(<vscale x 16 x i8> zeroinitializer, <vscale x 16 x i8> %data.xor)
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@davemgreen davemgreen Jun 4, 2025

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You could add zero RHS variants for SVE too.

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@rj-jesus rj-jesus Jun 5, 2025

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Thanks, done. :)

ret <vscale x 16 x i8> %data.aes
}

define <vscale x 16 x i8> @combineXorAesdZeroSVE(<vscale x 16 x i8> %data, <vscale x 16 x i8> %key) {
; CHECK-LABEL: define <vscale x 16 x i8> @combineXorAesdZeroSVE(
; CHECK-SAME: <vscale x 16 x i8> [[DATA:%.*]], <vscale x 16 x i8> [[KEY:%.*]]) {
; CHECK-NEXT: [[DATA_AES:%.*]] = tail call <vscale x 16 x i8> @llvm.aarch64.sve.aesd(<vscale x 16 x i8> [[DATA]], <vscale x 16 x i8> [[KEY]])
; CHECK-NEXT: ret <vscale x 16 x i8> [[DATA_AES]]
;
%data.xor = xor <vscale x 16 x i8> %data, %key
%data.aes = tail call <vscale x 16 x i8> @llvm.aarch64.sve.aesd(<vscale x 16 x i8> zeroinitializer, <vscale x 16 x i8> %data.xor)
ret <vscale x 16 x i8> %data.aes
}

declare <vscale x 16 x i8> @llvm.aarch64.sve.aese(<vscale x 16 x i8>, <vscale x 16 x i8>) #0
declare <vscale x 16 x i8> @llvm.aarch64.sve.aesd(<vscale x 16 x i8>, <vscale x 16 x i8>) #0
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