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[SiFive][RISCV] Remove VMConstraint from XSfvqmaccqoq and XSfvfwmaccqqq instructions. #142914

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Merged
merged 1 commit into from
Jun 5, 2025
Merged

[SiFive][RISCV] Remove VMConstraint from XSfvqmaccqoq and XSfvfwmaccqqq instructions. #142914

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2 changes: 2 additions & 0 deletions llvm/lib/Target/RISCV/RISCVInstrFormats.td
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Original file line number Diff line number Diff line change
Expand Up @@ -99,6 +99,8 @@ def VMConstraint : RISCVVConstraint<0b100>;
//
// * vcompress: The destination vector register group cannot overlap the
// source vector register group or the source mask register
def WidenVNoMask : RISCVVConstraint<!or(VS2Constraint.Value,
VS1Constraint.Value)>;
def WidenV : RISCVVConstraint<!or(VS2Constraint.Value,
VS1Constraint.Value,
VMConstraint.Value)>;
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4 changes: 2 additions & 2 deletions llvm/lib/Target/RISCV/RISCVInstrInfoXSf.td
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Expand Up @@ -208,15 +208,15 @@ let Predicates = [HasVendorXSfvqmaccdod], DecoderNamespace = "XSfvector",
}

let Predicates = [HasVendorXSfvqmaccqoq], DecoderNamespace = "XSfvector",
DestEEW = EEWSEWx4, RVVConstraint=WidenV in {
DestEEW = EEWSEWx4, RVVConstraint=WidenVNoMask in {
def VQMACCU_4x8x4 : CustomSiFiveVMACC<0b111100, OPMVV, "sf.vqmaccu.4x8x4">;
def VQMACC_4x8x4 : CustomSiFiveVMACC<0b111101, OPMVV, "sf.vqmacc.4x8x4">;
def VQMACCUS_4x8x4 : CustomSiFiveVMACC<0b111110, OPMVV, "sf.vqmaccus.4x8x4">;
def VQMACCSU_4x8x4 : CustomSiFiveVMACC<0b111111, OPMVV, "sf.vqmaccsu.4x8x4">;
}

let Predicates = [HasVendorXSfvfwmaccqqq], DecoderNamespace = "XSfvector",
DestEEW = EEWSEWx2, RVVConstraint=WidenV in {
DestEEW = EEWSEWx2, RVVConstraint=WidenVNoMask in {
def VFWMACC_4x4x4 : CustomSiFiveVMACC<0b111100, OPFVV, "sf.vfwmacc.4x4x4">;
}

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6 changes: 6 additions & 0 deletions llvm/test/MC/RISCV/rvv/xsfvfwmacc.s
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Expand Up @@ -13,3 +13,9 @@ sf.vfwmacc.4x4x4 v8, v4, v20
# CHECK-ENCODING: [0x5b,0x14,0x42,0xf3]
# CHECK-ERROR: instruction requires the following: 'XSfvfwmaccqqq' (SiFive Matrix Multiply Accumulate Instruction and 4-by-4))
# CHECK-UNKNOWN: f342145b <unknown>

sf.vfwmacc.4x4x4 v0, v4, v20
# CHECK-INST: sf.vfwmacc.4x4x4 v0, v4, v20
# CHECK-ENCODING: [0x5b,0x10,0x42,0xf3]
# CHECK-ERROR: instruction requires the following: 'XSfvfwmaccqqq' (SiFive Matrix Multiply Accumulate Instruction and 4-by-4))
# CHECK-UNKNOWN: f342105b <unknown>
6 changes: 6 additions & 0 deletions llvm/test/MC/RISCV/rvv/xsfvqmacc.s
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Expand Up @@ -55,3 +55,9 @@ sf.vqmaccsu.4x8x4 v8, v4, v20
# CHECK-ENCODING: [0x5b,0x24,0x42,0xff]
# CHECK-ERROR: instruction requires the following: 'XSfvqmaccqoq' (SiFive Int8 Matrix Multiplication Instructions (4-by-8 and 8-by-4))
# CHECK-UNKNOWN: ff42245b <unknown>

sf.vqmaccu.4x8x4 v0, v4, v20
# CHECK-INST: sf.vqmaccu.4x8x4 v0, v4, v20
# CHECK-ENCODING: [0x5b,0x20,0x42,0xf3]
# CHECK-ERROR: instruction requires the following: 'XSfvqmaccqoq' (SiFive Int8 Matrix Multiplication Instructions (4-by-8 and 8-by-4))
# CHECK-UNKNOWN: f342205b <unknown>
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