Skip to content

[MIRParser] Report register class errors in a deterministic order #142928

New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Merged
jayfoad merged 1 commit into from
Jun 6, 2025
Merged

[MIRParser] Report register class errors in a deterministic order #142928

Show file tree
Hide file tree
Changes from all commits
Commits
Show all changes
1 commit
Select commit
File filter

Filter by extension

Filter by extension
Conversations
Failed to load comments.
Loading
Jump to
Jump to file
Failed to load files.
Loading
Diff view
Diff view
28 changes: 19 additions & 9 deletions llvm/lib/CodeGen/MIRParser/MIRParser.cpp
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -763,22 +763,25 @@ bool MIRParserImpl::setupRegisterInfo(const PerFunctionMIParsingState &PFS,
MachineRegisterInfo &MRI = MF.getRegInfo();
const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo();

bool Error = false;
SmallVector<std::string> Errors;

// Create VRegs
auto populateVRegInfo = [&](const VRegInfo &Info, const Twine &Name) {
Register Reg = Info.VReg;
switch (Info.Kind) {
case VRegInfo::UNKNOWN:
error(Twine("Cannot determine class/bank of virtual register ") +
Name + " in function '" + MF.getName() + "'");
Error = true;
Errors.push_back(
(Twine("Cannot determine class/bank of virtual register ") + Name +
" in function '" + MF.getName() + "'")
.str());
break;
case VRegInfo::NORMAL:
if (!Info.D.RC->isAllocatable()) {
error(Twine("Cannot use non-allocatable class '") +
TRI->getRegClassName(Info.D.RC) + "' for virtual register " +
Name + " in function '" + MF.getName() + "'");
Error = true;
Errors.push_back((Twine("Cannot use non-allocatable class '") +
TRI->getRegClassName(Info.D.RC) +
"' for virtual register " + Name + " in function '" +
MF.getName() + "'")
.str());
break;
}

Expand Down Expand Up @@ -820,7 +823,14 @@ bool MIRParserImpl::setupRegisterInfo(const PerFunctionMIParsingState &PFS,
}
}

return Error;
if (Errors.empty())
return false;

// Report errors in a deterministic order.
sort(Errors);
for (auto &E : Errors)
error(E);
return true;
}

bool MIRParserImpl::initializeFrameInfo(PerFunctionMIParsingState &PFS,
Expand Down
7 changes: 3 additions & 4 deletions llvm/test/CodeGen/MIR/AMDGPU/virtreg-uses-unallocatable-class.mir
View file
Open in desktop
Original file line number Diff line number Diff line change
@@ -1,14 +1,13 @@
# UNSUPPORTED: reverse_iteration
# RUN: not llc -mtriple=amdgcn-- -mcpu=gfx900 -run-pass=none -o - %s 2>&1 | FileCheck %s

# Check a diagnostic is emitted if non-allocatable classes are used
# with virtual registers, and there's no assert.

# CHECK: error: {{.*}}: Cannot use non-allocatable class 'TTMP_32' for virtual register named_use in function 'virtreg_unallocatable'
# CHECK: error: {{.*}}: Cannot use non-allocatable class 'TTMP_32' for virtual register named_def in function 'virtreg_unallocatable'
# CHECK: error: {{.*}}: Cannot use non-allocatable class 'TTMP_32' for virtual register 0 in function 'virtreg_unallocatable'
# CHECK: error: {{.*}}: Cannot use non-allocatable class 'TTMP_32' for virtual register 2 in function 'virtreg_unallocatable'
# CHECK: error: {{.*}}: Cannot use non-allocatable class 'TTMP_32' for virtual register 1 in function 'virtreg_unallocatable'
# CHECK: error: {{.*}}: Cannot use non-allocatable class 'TTMP_32' for virtual register 2 in function 'virtreg_unallocatable'
# CHECK: error: {{.*}}: Cannot use non-allocatable class 'TTMP_32' for virtual register named_def in function 'virtreg_unallocatable'
# CHECK: error: {{.*}}: Cannot use non-allocatable class 'TTMP_32' for virtual register named_use in function 'virtreg_unallocatable'

---
name: virtreg_unallocatable
Expand Down
Loading