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[TableGen] Use contains instead of count. NFC. #143156

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jayfoad merged 2 commits into from
Jun 7, 2025
Merged

[TableGen] Use contains instead of count. NFC. #143156

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dafde63
[TableGen] Use `contains` instead of `count`. NFC.
jayfoad Jun 6, 2025
f021c15
s/int/bool/
jayfoad Jun 6, 2025
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5 changes: 3 additions & 2 deletions llvm/utils/TableGen/Basic/DirectiveEmitter.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -642,7 +642,8 @@ static void emitLeafTable(const DirectiveLanguage &DirLang, raw_ostream &OS,
auto &LeavesB = LeafTable[B];
int DirA = LeavesA[0], DirB = LeavesB[0];
// First of all, end directives compare greater than non-end directives.
int IsEndA = EndDirectives.count(DirA), IsEndB = EndDirectives.count(DirB);
int IsEndA = EndDirectives.contains(DirA);
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@jurahul jurahul Jun 6, 2025

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nit: make these bool?

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@jayfoad jayfoad Jun 6, 2025

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I assumed they were deliberately int because of IsEndA < IsEndB below, which would look a bit unusual if they were bool.

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@jurahul jurahul Jun 6, 2025

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I think in C++ < operator for bools is defined the natural way: Google search AI overview:

This behavior is consistent with the numerical interpretation of false and true as 0 and 1, respectively

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@jayfoad jayfoad Jun 6, 2025

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Fair enough. Done.

int IsEndB = EndDirectives.contains(DirB);
if (IsEndA != IsEndB)
return IsEndA < IsEndB;
if (LeavesA[1] == 0 && LeavesB[1] == 0)
Expand Down Expand Up @@ -682,7 +683,7 @@ static void emitLeafTable(const DirectiveLanguage &DirLang, raw_ostream &OS,

// Emit a marker where the first "end directive" is.
auto FirstE = find_if(Ordering, [&](int RowIdx) {
return EndDirectives.count(LeafTable[RowIdx][0]);
return EndDirectives.contains(LeafTable[RowIdx][0]);
});
OS << "[[maybe_unused]] static auto " << TableName
<< "EndDirective = " << TableName << " + "
Expand Down
8 changes: 4 additions & 4 deletions llvm/utils/TableGen/Common/CodeGenDAGPatterns.cpp
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Expand Up @@ -730,8 +730,8 @@ bool TypeInfer::EnforceSameNumElts(TypeSetByHwMode &V, TypeSetByHwMode &W) {
// processed identically.
auto NoLength = [](const SmallDenseSet<ElementCount> &Lengths,
MVT T) -> bool {
return !Lengths.count(T.isVector() ? T.getVectorElementCount()
: ElementCount());
return !Lengths.contains(T.isVector() ? T.getVectorElementCount()
: ElementCount());
};

SmallVector<unsigned, 4> Modes;
Expand Down Expand Up @@ -778,7 +778,7 @@ bool TypeInfer::EnforceSameSize(TypeSetByHwMode &A, TypeSetByHwMode &B) {
typedef SmallSet<TypeSize, 2, TypeSizeComparator> TypeSizeSet;

auto NoSize = [](const TypeSizeSet &Sizes, MVT T) -> bool {
return !Sizes.count(T.getSizeInBits());
return !Sizes.contains(T.getSizeInBits());
};

SmallVector<unsigned, 4> Modes;
Expand Down Expand Up @@ -3331,7 +3331,7 @@ void CodeGenDAGPatterns::ParsePatternFragments(bool OutFrags) {
auto ArgsCopy = Args;
SmallDenseSet<StringRef, 4> OperandsSet(llvm::from_range, ArgsCopy);

if (OperandsSet.count(""))
if (OperandsSet.contains(""))
P->error("Cannot have unnamed 'node' values in pattern fragment!");

// Parse the operands list.
Expand Down
8 changes: 4 additions & 4 deletions llvm/utils/TableGen/Common/CodeGenRegisters.cpp
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Expand Up @@ -1532,7 +1532,7 @@ void CodeGenRegBank::computeComposites() {
if (CodeGenSubRegIndex *Prev =
Idx1->addComposite(Idx2, Idx3, getHwModes())) {
// If the composition was not user-defined, always emit a warning.
if (!UserDefined.count({Idx1, Idx2}) ||
if (!UserDefined.contains({Idx1, Idx2}) ||
agree(compose(Idx1, Idx2), SubRegAction.at(Idx3)))
PrintWarning(Twine("SubRegIndex ") + Idx1->getQualifiedName() +
" and " + Idx2->getQualifiedName() +
Expand Down Expand Up @@ -2408,7 +2408,7 @@ void CodeGenRegBank::inferMatchingSuperRegClass(
if (RC->getSubClassWithSubReg(SubIdx) != RC)
continue;

if (ImpliedSubRegIndices.count(SubIdx))
if (ImpliedSubRegIndices.contains(SubIdx))
continue;

// Build list of (Sub, Super) pairs for this SubIdx, sorted by Sub. Note
Expand Down Expand Up @@ -2639,13 +2639,13 @@ CodeGenRegBank::computeCoveredRegisters(ArrayRef<const Record *> Regs) {
// Second, find all super-registers that are completely covered by the set.
for (unsigned i = 0; i != Set.size(); ++i) {
for (const CodeGenRegister *Super : Set[i]->getSuperRegs()) {
if (!Super->CoveredBySubRegs || Set.count(Super))
if (!Super->CoveredBySubRegs || Set.contains(Super))
continue;
// This new super-register is covered by its sub-registers.
bool AllSubsInSet = true;
const CodeGenRegister::SubRegMap &SRM = Super->getSubRegs();
for (auto [_, SR] : SRM)
if (!Set.count(SR)) {
if (!Set.contains(SR)) {
AllSubsInSet = false;
break;
}
Expand Down
4 changes: 2 additions & 2 deletions llvm/utils/TableGen/Common/CodeGenSchedule.cpp
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Expand Up @@ -1637,7 +1637,7 @@ static void inferFromTransitions(ArrayRef<PredTransition> LastTransitions,
// Transition should not contain processor indices already assigned to
// InstRWs in this scheduling class.
const CodeGenSchedClass &FromSC = SchedModels.getSchedClass(FromClassIdx);
if (FromSC.InstRWProcIndices.count(LastTransition.ProcIndex))
if (FromSC.InstRWProcIndices.contains(LastTransition.ProcIndex))
continue;
SCTrans.ProcIndex = LastTransition.ProcIndex;
SCTrans.ToClassIdx =
Expand Down Expand Up @@ -2176,7 +2176,7 @@ bool CodeGenProcModel::isUnsupported(const CodeGenInstruction &Inst) const {
}

bool CodeGenProcModel::hasReadOfWrite(const Record *WriteDef) const {
return ReadOfWriteSet.count(WriteDef);
return ReadOfWriteSet.contains(WriteDef);
}

#ifndef NDEBUG
Expand Down
2 changes: 1 addition & 1 deletion llvm/utils/TableGen/Common/GlobalISel/GlobalISelMatchTable.h
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Expand Up @@ -1400,7 +1400,7 @@ class InstructionOpcodeMatcher : public InstructionPredicateMatcher {
}

bool hasValue() const override {
return Insts.size() == 1 && OpcodeValues.count(Insts[0]);
return Insts.size() == 1 && OpcodeValues.contains(Insts[0]);
}

// TODO: This is used for the SwitchMatcher optimization. We should be able to
Expand Down
4 changes: 2 additions & 2 deletions llvm/utils/TableGen/Common/GlobalISel/Patterns.cpp
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Expand Up @@ -581,7 +581,7 @@ bool PatFrag::checkSemantics() {

StringSet<> SeenOps;
for (const auto &Op : in_params()) {
if (SeenOps.count(Op.Name)) {
if (SeenOps.contains(Op.Name)) {
PrintError("duplicate parameter '" + Op.Name + "'");
return false;
}
Expand Down Expand Up @@ -609,7 +609,7 @@ bool PatFrag::checkSemantics() {
return false;
}

if (SeenOps.count(Op.Name)) {
if (SeenOps.contains(Op.Name)) {
PrintError("duplicate parameter '" + Op.Name + "'");
return false;
}
Expand Down
2 changes: 1 addition & 1 deletion llvm/utils/TableGen/GlobalISelCombinerEmitter.cpp
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Expand Up @@ -1161,7 +1161,7 @@ bool CombineRuleBuilder::buildPermutationsToEmit() {
PermutationsToEmit.clear();

for (const auto &Perm : CurPerms) {
assert(!Perm.count(Pat.get()) && "Pattern already emitted?");
assert(!Perm.contains(Pat.get()) && "Pattern already emitted?");
for (unsigned K = 0; K < NumAlts; ++K) {
PatternAlternatives NewPerm = Perm;
NewPerm[Pat.get()] = K;
Expand Down
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