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[SPARC][IAS] Properly set implied feature sets for ISA levels/extensions #143232

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Merged
merged 4 commits into from
Jun 19, 2025
Merged

[SPARC][IAS] Properly set implied feature sets for ISA levels/extensions #143232

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e0d2634
[SPARC][IAS] Make Is64Bit imply FeatureV9 in the assembler
koachan Jun 7, 2025
492495d
Apply suggestions for error checks
koachan Jun 8, 2025
995cc68
Also add implied featureset for other ISA extensions
koachan Jun 8, 2025
58154ca
Apply feedback on tests
koachan Jun 15, 2025
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18 changes: 12 additions & 6 deletions llvm/lib/Target/Sparc/Sparc.td
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Original file line number Diff line number Diff line change
Expand Up @@ -42,22 +42,28 @@ def FeatureV8Deprecated
"Enable deprecated V8 instructions in V9 mode">;
def FeatureVIS
: SubtargetFeature<"vis", "IsVIS", "true",
"Enable UltraSPARC Visual Instruction Set extensions">;
"Enable UltraSPARC Visual Instruction Set extensions",
[FeatureV9]>;
def FeatureVIS2
: SubtargetFeature<"vis2", "IsVIS2", "true",
"Enable Visual Instruction Set extensions II">;
"Enable Visual Instruction Set extensions II",
[FeatureV9]>;
def FeatureVIS3
: SubtargetFeature<"vis3", "IsVIS3", "true",
"Enable Visual Instruction Set extensions III">;
"Enable Visual Instruction Set extensions III",
[FeatureV9]>;
def FeatureUA2005
: SubtargetFeature<"ua2005", "IsUA2005", "true",
"Enable UltraSPARC Architecture 2005 extensions">;
"Enable UltraSPARC Architecture 2005 extensions",
[FeatureV9, FeatureVIS, FeatureVIS2]>;
def FeatureUA2007
: SubtargetFeature<"ua2007", "IsUA2007", "true",
"Enable UltraSPARC Architecture 2007 extensions">;
"Enable UltraSPARC Architecture 2007 extensions",
[FeatureV9, FeatureVIS, FeatureVIS2]>;
def FeatureOSA2011
: SubtargetFeature<"osa2011", "IsOSA2011", "true",
"Enable Oracle SPARC Architecture 2011 extensions">;
"Enable Oracle SPARC Architecture 2011 extensions",
[FeatureV9, FeatureVIS, FeatureVIS2, FeatureVIS3]>;
def FeatureLeon
: SubtargetFeature<"leon", "IsLeon", "true",
"Enable LEON extensions">;
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3 changes: 2 additions & 1 deletion llvm/lib/Target/Sparc/SparcInstrInfo.td
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Expand Up @@ -24,7 +24,8 @@ include "SparcInstrFormats.td"
def Is32Bit : Predicate<"!Subtarget->is64Bit()">;

// True when generating 64-bit code. This also implies HasV9.
def Is64Bit : Predicate<"Subtarget->is64Bit()">;
def Is64Bit : Predicate<"Subtarget->is64Bit()">,
AssemblerPredicate<(all_of FeatureV9)>;

def UseSoftMulDiv : Predicate<"Subtarget->useSoftMulDiv()">,
AssemblerPredicate<(all_of FeatureSoftMulDiv)>;
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42 changes: 16 additions & 26 deletions llvm/test/CodeGen/SPARC/ctlz.ll
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Expand Up @@ -207,20 +207,15 @@ define i64 @i64_nopoison(i64 %x) nounwind {
;
; SPARC-VIS3-LABEL: i64_nopoison:
; SPARC-VIS3: ! %bb.0:
; SPARC-VIS3-NEXT: srl %o0, 0, %o2
; SPARC-VIS3-NEXT: lzcnt %o2, %o2
; SPARC-VIS3-NEXT: add %o2, -32, %o2
; SPARC-VIS3-NEXT: srl %o1, 0, %o1
; SPARC-VIS3-NEXT: lzcnt %o1, %o1
; SPARC-VIS3-NEXT: add %o1, -32, %o1
; SPARC-VIS3-NEXT: add %o1, 32, %o1
; SPARC-VIS3-NEXT: cmp %o0, 0
; SPARC-VIS3-NEXT: bne .LBB2_2
; SPARC-VIS3-NEXT: nop
; SPARC-VIS3-NEXT: ! %bb.1:
; SPARC-VIS3-NEXT: srl %o1, 0, %o0
; SPARC-VIS3-NEXT: lzcnt %o0, %o0
; SPARC-VIS3-NEXT: add %o0, -32, %o0
; SPARC-VIS3-NEXT: add %o0, 32, %o1
; SPARC-VIS3-NEXT: retl
; SPARC-VIS3-NEXT: mov %g0, %o0
; SPARC-VIS3-NEXT: .LBB2_2:
; SPARC-VIS3-NEXT: srl %o0, 0, %o0
; SPARC-VIS3-NEXT: lzcnt %o0, %o0
; SPARC-VIS3-NEXT: add %o0, -32, %o1
; SPARC-VIS3-NEXT: movne %icc, %o2, %o1
; SPARC-VIS3-NEXT: retl
; SPARC-VIS3-NEXT: mov %g0, %o0
;
Expand Down Expand Up @@ -311,20 +306,15 @@ define i64 @i64_poison(i64 %x) nounwind {
;
; SPARC-VIS3-LABEL: i64_poison:
; SPARC-VIS3: ! %bb.0:
; SPARC-VIS3-NEXT: srl %o0, 0, %o2
; SPARC-VIS3-NEXT: lzcnt %o2, %o2
; SPARC-VIS3-NEXT: add %o2, -32, %o2
; SPARC-VIS3-NEXT: srl %o1, 0, %o1
; SPARC-VIS3-NEXT: lzcnt %o1, %o1
; SPARC-VIS3-NEXT: add %o1, -32, %o1
; SPARC-VIS3-NEXT: add %o1, 32, %o1
; SPARC-VIS3-NEXT: cmp %o0, 0
; SPARC-VIS3-NEXT: bne .LBB3_2
; SPARC-VIS3-NEXT: nop
; SPARC-VIS3-NEXT: ! %bb.1:
; SPARC-VIS3-NEXT: srl %o1, 0, %o0
; SPARC-VIS3-NEXT: lzcnt %o0, %o0
; SPARC-VIS3-NEXT: add %o0, -32, %o0
; SPARC-VIS3-NEXT: add %o0, 32, %o1
; SPARC-VIS3-NEXT: retl
; SPARC-VIS3-NEXT: mov %g0, %o0
; SPARC-VIS3-NEXT: .LBB3_2:
; SPARC-VIS3-NEXT: srl %o0, 0, %o0
; SPARC-VIS3-NEXT: lzcnt %o0, %o0
; SPARC-VIS3-NEXT: add %o0, -32, %o1
; SPARC-VIS3-NEXT: movne %icc, %o2, %o1
; SPARC-VIS3-NEXT: retl
; SPARC-VIS3-NEXT: mov %g0, %o0
;
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46 changes: 20 additions & 26 deletions llvm/test/CodeGen/SPARC/cttz.ll
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Expand Up @@ -254,28 +254,25 @@ define i64 @i64_nopoison(i64 %x) nounwind {
;
; SPARC-VIS3-LABEL: i64_nopoison:
; SPARC-VIS3: ! %bb.0:
; SPARC-VIS3-NEXT: cmp %o1, 0
; SPARC-VIS3-NEXT: bne .LBB2_2
; SPARC-VIS3-NEXT: nop
; SPARC-VIS3-NEXT: ! %bb.1:
; SPARC-VIS3-NEXT: add %o0, -1, %o1
; SPARC-VIS3-NEXT: andn %o1, %o0, %o0
; SPARC-VIS3-NEXT: add %o0, -1, %o2
; SPARC-VIS3-NEXT: andn %o2, %o0, %o0
; SPARC-VIS3-NEXT: srl %o0, 0, %o0
; SPARC-VIS3-NEXT: lzcnt %o0, %o0
; SPARC-VIS3-NEXT: add %o0, -32, %o0
; SPARC-VIS3-NEXT: ba .LBB2_3
; SPARC-VIS3-NEXT: mov 64, %o1
; SPARC-VIS3-NEXT: .LBB2_2:
; SPARC-VIS3-NEXT: mov 64, %o2
; SPARC-VIS3-NEXT: sub %o2, %o0, %o2
; SPARC-VIS3-NEXT: add %o1, -1, %o0
; SPARC-VIS3-NEXT: andn %o0, %o1, %o0
; SPARC-VIS3-NEXT: srl %o0, 0, %o0
; SPARC-VIS3-NEXT: lzcnt %o0, %o0
; SPARC-VIS3-NEXT: add %o0, -32, %o0
; SPARC-VIS3-NEXT: mov 32, %o1
; SPARC-VIS3-NEXT: .LBB2_3:
; SPARC-VIS3-NEXT: sub %o1, %o0, %o1
; SPARC-VIS3-NEXT: retl
; SPARC-VIS3-NEXT: mov 32, %o3
; SPARC-VIS3-NEXT: sub %o3, %o0, %o0
; SPARC-VIS3-NEXT: cmp %o1, 0
; SPARC-VIS3-NEXT: movne %icc, %o0, %o2
; SPARC-VIS3-NEXT: mov %g0, %o0
; SPARC-VIS3-NEXT: retl
; SPARC-VIS3-NEXT: mov %o2, %o1
;
; SPARC64-LABEL: i64_nopoison:
; SPARC64: ! %bb.0:
Expand Down Expand Up @@ -376,28 +373,25 @@ define i64 @i64_poison(i64 %x) nounwind {
;
; SPARC-VIS3-LABEL: i64_poison:
; SPARC-VIS3: ! %bb.0:
; SPARC-VIS3-NEXT: cmp %o1, 0
; SPARC-VIS3-NEXT: bne .LBB3_2
; SPARC-VIS3-NEXT: nop
; SPARC-VIS3-NEXT: ! %bb.1:
; SPARC-VIS3-NEXT: add %o0, -1, %o1
; SPARC-VIS3-NEXT: andn %o1, %o0, %o0
; SPARC-VIS3-NEXT: add %o0, -1, %o2
; SPARC-VIS3-NEXT: andn %o2, %o0, %o0
; SPARC-VIS3-NEXT: srl %o0, 0, %o0
; SPARC-VIS3-NEXT: lzcnt %o0, %o0
; SPARC-VIS3-NEXT: add %o0, -32, %o0
; SPARC-VIS3-NEXT: ba .LBB3_3
; SPARC-VIS3-NEXT: mov 64, %o1
; SPARC-VIS3-NEXT: .LBB3_2:
; SPARC-VIS3-NEXT: mov 64, %o2
; SPARC-VIS3-NEXT: sub %o2, %o0, %o2
; SPARC-VIS3-NEXT: add %o1, -1, %o0
; SPARC-VIS3-NEXT: andn %o0, %o1, %o0
; SPARC-VIS3-NEXT: srl %o0, 0, %o0
; SPARC-VIS3-NEXT: lzcnt %o0, %o0
; SPARC-VIS3-NEXT: add %o0, -32, %o0
; SPARC-VIS3-NEXT: mov 32, %o1
; SPARC-VIS3-NEXT: .LBB3_3:
; SPARC-VIS3-NEXT: sub %o1, %o0, %o1
; SPARC-VIS3-NEXT: retl
; SPARC-VIS3-NEXT: mov 32, %o3
; SPARC-VIS3-NEXT: sub %o3, %o0, %o0
; SPARC-VIS3-NEXT: cmp %o1, 0
; SPARC-VIS3-NEXT: movne %icc, %o0, %o2
; SPARC-VIS3-NEXT: mov %g0, %o0
; SPARC-VIS3-NEXT: retl
; SPARC-VIS3-NEXT: mov %o2, %o1
;
; SPARC64-LABEL: i64_poison:
; SPARC64: ! %bb.0:
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9 changes: 9 additions & 0 deletions llvm/test/CodeGen/SPARC/inlineasm-v9.ll
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Expand Up @@ -58,3 +58,12 @@ Entry:
tail call void asm sideeffect "", "{o0}"(i64 %val)
ret void
}

; CHECK-LABEL: test_twinword:
; CHECK: rd %pc, %i1
; CHECK: srlx %i1, 32, %i0

define i64 @test_twinword(){
%1 = tail call i64 asm sideeffect "rd %asr5, ${0:L} \0A\09 srlx ${0:L}, 32, ${0:H}", "={i0}"()
ret i64 %1
}
9 changes: 0 additions & 9 deletions llvm/test/CodeGen/SPARC/inlineasm.ll
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Expand Up @@ -144,15 +144,6 @@ entry:
ret void
}

; CHECK-LABEL: test_twinword:
; CHECK: rd %asr5, %i1
; CHECK: srlx %i1, 32, %i0

define i64 @test_twinword(){
%1 = tail call i64 asm sideeffect "rd %asr5, ${0:L} \0A\09 srlx ${0:L}, 32, ${0:H}", "={i0}"()
ret i64 %1
}

; CHECK-LABEL: test_symbol:
; CHECK: ba,a brtarget
define void @test_symbol() {
Expand Down
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