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6 changes: 6 additions & 0 deletions compiler-rt/lib/builtins/cpu_model/riscv.c
Original file line number Diff line number Diff line change
Expand Up @@ -24,12 +24,18 @@ struct {
// TODO: Maybe generate a header from tablegen then include it.
#define A_GROUPID 0
#define A_BITMASK (1ULL << 0)
#define B_GROUPID 0
#define B_BITMASK (1ULL << 1)
#define C_GROUPID 0
#define C_BITMASK (1ULL << 2)
#define D_GROUPID 0
#define D_BITMASK (1ULL << 3)
#define E_GROUPID 0
#define E_BITMASK (1ULL << 4)
#define F_GROUPID 0
#define F_BITMASK (1ULL << 5)
#define H_GROUPID 0
#define H_BITMASK (1ULL << 7)
#define I_GROUPID 0
#define I_BITMASK (1ULL << 8)
#define M_GROUPID 0
Expand Down
10 changes: 6 additions & 4 deletions llvm/lib/Target/RISCV/RISCVFeatures.td
Original file line number Diff line number Diff line change
Expand Up @@ -75,7 +75,8 @@ def FeatureStdExtI
RISCVExtensionBitmask<0, 8>;

def FeatureStdExtE
: RISCVExtension<2, 0, "Embedded Instruction Set with 16 GPRs">;
: RISCVExtension<2, 0, "Embedded Instruction Set with 16 GPRs">,
RISCVExtensionBitmask<0, 4>;

def FeatureStdExtZic64b
: RISCVExtension<1, 0, "Cache Block Size Is 64 Bytes">;
Expand Down Expand Up @@ -510,7 +511,8 @@ def HasStdExtZbs : Predicate<"Subtarget->hasStdExtZbs()">,

def FeatureStdExtB
: RISCVExtension<1, 0, "the collection of the Zba, Zbb, Zbs extensions",
[FeatureStdExtZba, FeatureStdExtZbb, FeatureStdExtZbs]>;
[FeatureStdExtZba, FeatureStdExtZbb, FeatureStdExtZbs]>,
RISCVExtensionBitmask<0, 1>;

def FeatureStdExtZbkb
: RISCVExtension<1, 0, "Bitmanip instructions for Cryptography">,
Expand Down Expand Up @@ -887,8 +889,8 @@ def HasVInstructionsFullMultiply : Predicate<"Subtarget->hasVInstructionsFullMul

// Hypervisor Extensions

def FeatureStdExtH : RISCVExtension<1, 0, "Hypervisor">;

def FeatureStdExtH : RISCVExtension<1, 0, "Hypervisor">,
RISCVExtensionBitmask<0, 7>;
def HasStdExtH : Predicate<"Subtarget->hasStdExtH()">,
AssemblerPredicate<(all_of FeatureStdExtH),
"'H' (Hypervisor)">;
Expand Down
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