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[RISCV] Efficiently lower (select cond, u, rot[r/l](u, rot.amt)) using zicond extension #143768

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Merged
merged 1 commit into from
Jul 3, 2025
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[RISCV] Efficiently lower (select cond, u, rot[r/l](u, rot.amt)) using zicond extension #143768

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4 changes: 4 additions & 0 deletions llvm/lib/Target/RISCV/RISCVISelLowering.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -18339,6 +18339,8 @@ static bool combine_CC(SDValue &LHS, SDValue &RHS, SDValue &CC, const SDLoc &DL,
// (select C, (sub Y, X), Y) -> (sub Y, (select C, X, 0)).
// (select C, (or Y, X), Y) -> (or Y, (select C, X, 0)).
// (select C, (xor Y, X), Y) -> (xor Y, (select C, X, 0)).
// (select C, (rotl Y, X), Y) -> (rotl Y, (select C, X, 0)).
// (select C, (rotr Y, X), Y) -> (rotr Y, (select C, X, 0)).
static SDValue tryFoldSelectIntoOp(SDNode *N, SelectionDAG &DAG,
SDValue TrueVal, SDValue FalseVal,
bool Swapped) {
Expand All @@ -18351,6 +18353,8 @@ static SDValue tryFoldSelectIntoOp(SDNode *N, SelectionDAG &DAG,
case ISD::SRA:
case ISD::SRL:
case ISD::SUB:
case ISD::ROTL:
case ISD::ROTR:
Commutative = false;
break;
case ISD::ADD:
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82 changes: 34 additions & 48 deletions llvm/test/CodeGen/RISCV/zicond-opts.ll
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Expand Up @@ -62,37 +62,30 @@ define i64 @rotate_l_nez(i64 %x, i64 %rot.amt, i1 %cond) {
; RV32ZICOND-LABEL: rotate_l_nez:
; RV32ZICOND: # %bb.0:
; RV32ZICOND-NEXT: andi a4, a4, 1
; RV32ZICOND-NEXT: bexti a3, a2, 5
; RV32ZICOND-NEXT: not a5, a2
; RV32ZICOND-NEXT: czero.nez a6, a1, a3
; RV32ZICOND-NEXT: czero.eqz a7, a0, a3
; RV32ZICOND-NEXT: czero.nez t0, a0, a3
; RV32ZICOND-NEXT: czero.eqz a3, a1, a3
; RV32ZICOND-NEXT: czero.eqz a0, a0, a4
; RV32ZICOND-NEXT: czero.eqz a1, a1, a4
; RV32ZICOND-NEXT: or a6, a7, a6
; RV32ZICOND-NEXT: or a3, a3, t0
; RV32ZICOND-NEXT: sll a7, a6, a2
; RV32ZICOND-NEXT: srli t0, a3, 1
; RV32ZICOND-NEXT: sll a2, a3, a2
; RV32ZICOND-NEXT: srli a3, a6, 1
; RV32ZICOND-NEXT: srl a6, t0, a5
; RV32ZICOND-NEXT: srl a3, a3, a5
; RV32ZICOND-NEXT: or a5, a7, a6
; RV32ZICOND-NEXT: or a2, a2, a3
; RV32ZICOND-NEXT: czero.nez a2, a2, a4
; RV32ZICOND-NEXT: czero.nez a3, a5, a4
; RV32ZICOND-NEXT: or a0, a0, a2
; RV32ZICOND-NEXT: or a1, a1, a3
; RV32ZICOND-NEXT: bexti a3, a2, 5
; RV32ZICOND-NEXT: czero.nez a4, a0, a3
; RV32ZICOND-NEXT: czero.eqz a5, a1, a3
; RV32ZICOND-NEXT: czero.nez a1, a1, a3
; RV32ZICOND-NEXT: czero.eqz a0, a0, a3
; RV32ZICOND-NEXT: not a3, a2
; RV32ZICOND-NEXT: or a4, a5, a4
; RV32ZICOND-NEXT: or a0, a0, a1
; RV32ZICOND-NEXT: sll a1, a4, a2
; RV32ZICOND-NEXT: srli a5, a0, 1
; RV32ZICOND-NEXT: sll a2, a0, a2
; RV32ZICOND-NEXT: srli a4, a4, 1
; RV32ZICOND-NEXT: srl a0, a5, a3
; RV32ZICOND-NEXT: srl a3, a4, a3
; RV32ZICOND-NEXT: or a0, a1, a0
; RV32ZICOND-NEXT: or a1, a2, a3
; RV32ZICOND-NEXT: ret
;
; RV64ZICOND-LABEL: rotate_l_nez:
; RV64ZICOND: # %bb.0:
; RV64ZICOND-NEXT: andi a2, a2, 1
; RV64ZICOND-NEXT: rol a1, a0, a1
; RV64ZICOND-NEXT: czero.nez a1, a1, a2
; RV64ZICOND-NEXT: czero.eqz a0, a0, a2
; RV64ZICOND-NEXT: or a0, a0, a1
; RV64ZICOND-NEXT: rol a0, a0, a1
; RV64ZICOND-NEXT: ret
%6 = call i64 @llvm.fshl.i64(i64 %x, i64 %x, i64 %rot.amt)
%7 = select i1 %cond, i64 %x, i64 %6
Expand All @@ -104,37 +97,30 @@ define i64 @rotate_l_eqz(i64 %x, i64 %rot.amt, i1 %cond) {
; RV32ZICOND-LABEL: rotate_l_eqz:
; RV32ZICOND: # %bb.0:
; RV32ZICOND-NEXT: andi a4, a4, 1
; RV32ZICOND-NEXT: bexti a3, a2, 5
; RV32ZICOND-NEXT: not a5, a2
; RV32ZICOND-NEXT: czero.nez a6, a1, a3
; RV32ZICOND-NEXT: czero.eqz a7, a0, a3
; RV32ZICOND-NEXT: czero.nez t0, a0, a3
; RV32ZICOND-NEXT: czero.eqz a3, a1, a3
; RV32ZICOND-NEXT: czero.nez a0, a0, a4
; RV32ZICOND-NEXT: czero.nez a1, a1, a4
; RV32ZICOND-NEXT: or a6, a7, a6
; RV32ZICOND-NEXT: or a3, a3, t0
; RV32ZICOND-NEXT: sll a7, a6, a2
; RV32ZICOND-NEXT: srli t0, a3, 1
; RV32ZICOND-NEXT: sll a2, a3, a2
; RV32ZICOND-NEXT: srli a3, a6, 1
; RV32ZICOND-NEXT: srl a6, t0, a5
; RV32ZICOND-NEXT: srl a3, a3, a5
; RV32ZICOND-NEXT: or a5, a7, a6
; RV32ZICOND-NEXT: or a2, a2, a3
; RV32ZICOND-NEXT: czero.eqz a2, a2, a4
; RV32ZICOND-NEXT: czero.eqz a3, a5, a4
; RV32ZICOND-NEXT: or a0, a2, a0
; RV32ZICOND-NEXT: or a1, a3, a1
; RV32ZICOND-NEXT: bexti a3, a2, 5
; RV32ZICOND-NEXT: czero.nez a4, a0, a3
; RV32ZICOND-NEXT: czero.eqz a5, a1, a3
; RV32ZICOND-NEXT: czero.nez a1, a1, a3
; RV32ZICOND-NEXT: czero.eqz a0, a0, a3
; RV32ZICOND-NEXT: not a3, a2
; RV32ZICOND-NEXT: or a4, a5, a4
; RV32ZICOND-NEXT: or a0, a0, a1
; RV32ZICOND-NEXT: sll a1, a4, a2
; RV32ZICOND-NEXT: srli a5, a0, 1
; RV32ZICOND-NEXT: sll a2, a0, a2
; RV32ZICOND-NEXT: srli a4, a4, 1
; RV32ZICOND-NEXT: srl a0, a5, a3
; RV32ZICOND-NEXT: srl a3, a4, a3
; RV32ZICOND-NEXT: or a0, a1, a0
; RV32ZICOND-NEXT: or a1, a2, a3
; RV32ZICOND-NEXT: ret
;
; RV64ZICOND-LABEL: rotate_l_eqz:
; RV64ZICOND: # %bb.0:
; RV64ZICOND-NEXT: andi a2, a2, 1
; RV64ZICOND-NEXT: rol a1, a0, a1
; RV64ZICOND-NEXT: czero.nez a0, a0, a2
; RV64ZICOND-NEXT: czero.eqz a1, a1, a2
; RV64ZICOND-NEXT: or a0, a1, a0
; RV64ZICOND-NEXT: rol a0, a0, a1
; RV64ZICOND-NEXT: ret
%6 = call i64 @llvm.fshl.i64(i64 %x, i64 %x, i64 %rot.amt)
%7 = select i1 %cond, i64 %6, i64 %x
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