Skip to content

[PowePC] using MTVSRBMI instruction instead of constant pool in power10+ #144084

New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Merged
merged 5 commits into from
Jul 4, 2025
Merged

[PowePC] using MTVSRBMI instruction instead of constant pool in power10+ #144084

Show file tree
Hide file tree
Changes from 1 commit
Commits
Show all changes
5 commits
Select commit Hold shift + click to select a range
31d4e3c
using MTVSRBMI instead of constant pool
diggerlin Jun 11, 2025
b5ac0bf
address comment
diggerlin Jun 18, 2025
a3a724a
address comment
diggerlin Jun 23, 2025
78e54f8
run git clang format
diggerlin Jun 24, 2025
1656ad2
git clang format
diggerlin Jun 25, 2025
File filter

Filter by extension

Filter by extension
Conversations
Failed to load comments.
Loading
Jump to
Jump to file
Failed to load files.
Loading
Diff view
Diff view
49 changes: 49 additions & 0 deletions llvm/lib/Target/PowerPC/PPCISelLowering.cpp
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -9580,6 +9580,37 @@ static bool isValidSplatLoad(const PPCSubtarget &Subtarget, const SDValue &Op,
return false;
}

bool isValidMtVsrbmi(APInt &BMI, BuildVectorSDNode &BVN) {
Copy link
Collaborator

@RolandF77 RolandF77 Jun 16, 2025

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

The instruction uses bmi but instruction names are short. Maybe use BitMask for parameter.

unsigned int NumOps = BVN.getNumOperands();
assert(NumOps > 0 && "isConstantSplat has 0-size build vector");
Copy link
Collaborator

@RolandF77 RolandF77 Jun 16, 2025

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

This assert text seems confusing. The routine is not called from isConstantSplat. Maybe just say unexpected 0 size build vector.


BMI.clearAllBits();
EVT VT = BVN.getValueType(0);
APInt ConstValue(VT.getSizeInBits(), 0);

unsigned EltWidth = VT.getScalarSizeInBits();

for (unsigned j = 0; j < NumOps; ++j) {
Copy link
Contributor

@lei137 lei137 Jun 13, 2025

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

Since BuildVectorSDNode is super class of SDNode, can we not use range based for loop to iterate over the operands?

Copy link
Collaborator

@RolandF77 RolandF77 Jun 16, 2025

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

The index is used.

Copy link
Collaborator

@RolandF77 RolandF77 Jun 16, 2025

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

This loop uses lowercase j, the loop below uppercase J. Let's pick one and stick with it.

SDValue OpVal = BVN.getOperand(j);
unsigned BitPos = j * EltWidth;
auto *CN = dyn_cast<ConstantSDNode>(OpVal);

if (!CN)
return false;

ConstValue.insertBits(CN->getAPIntValue().zextOrTrunc(EltWidth), BitPos);
}

for (unsigned J = 0; J < 16; J++) {
Copy link
Collaborator

@RolandF77 RolandF77 Jun 16, 2025

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

Let's stick with pre-increment like the above j loop.

APInt ExtractValue = ConstValue.extractBits(8, J * 8);
if (ExtractValue != 0x00 && ExtractValue != 0xFF)
return false;
if (ExtractValue == 0xFF)
BMI.setBit(J);
}
return true;
}

// If this is a case we can't handle, return null and let the default
// expansion code take care of it. If we CAN select this case, and if it
// selects to a single instruction, return Op. Otherwise, if we can codegen
Expand All @@ -9591,6 +9622,24 @@ SDValue PPCTargetLowering::LowerBUILD_VECTOR(SDValue Op,
BuildVectorSDNode *BVN = dyn_cast<BuildVectorSDNode>(Op.getNode());
assert(BVN && "Expected a BuildVectorSDNode in LowerBUILD_VECTOR");

if(Subtarget.hasP10Vector()) {
APInt BMI(32, 0);
// If the value of the vector is all zeros or all ones,
// we do not convert it to MTVSRBMI.
// The xxleqv instruction sets a vector with all ones.
// The xxlxor instruction sets a vector with all zeros.
if (isValidMtVsrbmi(BMI, *BVN) && BMI != 0 && BMI!=0xffff ) {
SDValue SDConstant= DAG.getTargetConstant(BMI, dl, MVT::i32);
Copy link
Collaborator

@RolandF77 RolandF77 Jun 16, 2025

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

Spacing looks off.

MachineSDNode* MSDNode = DAG.getMachineNode(PPC::MTVSRBMI, dl,MVT::v16i8, SDConstant);
Copy link
Collaborator

@RolandF77 RolandF77 Jun 16, 2025

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

Spacing.

Copy link
Collaborator

@RolandF77 RolandF77 Jun 18, 2025

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

Spacing around dl,MVT::v16i8 still looks off.

SDValue SDV = SDValue(MSDNode,0);
Copy link
Collaborator

@RolandF77 RolandF77 Jun 16, 2025

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

Spacing.

EVT DVT = BVN->getValueType(0);
EVT SVT = SDV.getValueType();
if (SVT != DVT ) {
SDV = DAG.getNode(ISD::BITCAST, dl, DVT, SDV);
Copy link
Contributor

@lei137 lei137 Jun 13, 2025

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

clang format

}
return SDV;
}
}
// Check if this is a splat of a constant value.
APInt APSplatBits, APSplatUndef;
unsigned SplatBitSize;
Expand Down
23 changes: 4 additions & 19 deletions llvm/test/CodeGen/PowerPC/mtvsrbmi.ll
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -10,28 +10,13 @@
; RUN: | FileCheck %s --check-prefix=CHECK

define dso_local noundef range(i8 -1, 1) <16 x i8> @_Z5v00FFv() {
; CHECK: L..CPI0_0:
; CHECK-NEXT: .byte 255 # 0xff
; CHECK-NEXT: .byte 0 # 0x0
; CHECK-NEXT: .byte 0 # 0x0
; CHECK-NEXT: .byte 0 # 0x0
; CHECK-NEXT: .byte 0 # 0x0
; CHECK-NEXT: .byte 0 # 0x0
; CHECK-NEXT: .byte 0 # 0x0
; CHECK-NEXT: .byte 0 # 0x0
; CHECK-NEXT: .byte 0 # 0x0
; CHECK-NEXT: .byte 0 # 0x0
; CHECK-NEXT: .byte 0 # 0x0
; CHECK-NEXT: .byte 0 # 0x0
; CHECK-NEXT: .byte 0 # 0x0
; CHECK-NEXT: .byte 0 # 0x0
; CHECK-NEXT: .byte 0 # 0x0
; CHECK-NEXT: .byte 0 # 0x0
; CHECK-NOT: L..CPI0_0:
; CHECK-NOT: .byte 255 # 0xff
; CHECK-NOT: .byte 0 # 0x0

; CHECK-LABEL: _Z5v00FFv:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lwz r3, L..C0(r2) # %const.0
; CHECK-NEXT: lxv vs34, 0(r3)
; CHECK-NEXT: mtvsrbmi v2, 1
; CHECK-NEXT: blr
entry:
ret <16 x i8> <i8 -1, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>
Expand Down
Loading