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[RISCV] Change input register type for QC_SWM and QC_SWMI #144294

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Merged
svs-quic merged 1 commit into from
Jun 16, 2025
Merged

[RISCV] Change input register type for QC_SWM and QC_SWMI #144294

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2 changes: 1 addition & 1 deletion llvm/docs/RISCVUsage.rst
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Expand Up @@ -487,7 +487,7 @@ The current vendor extensions supported are:
LLVM implements `version 0.3 of the Qualcomm uC Large Offset Load Store extension specification <https://github.com/quic/riscv-unified-db/releases/tag/Xqci-0.11.0>`__ by Qualcomm. These instructions are only available for riscv32.

``experimental-Xqcilsm``
LLVM implements `version 0.5 of the Qualcomm uC Load Store Multiple extension specification <https://github.com/quic/riscv-unified-db/releases/tag/Xqci-0.11.0>`__ by Qualcomm. These instructions are only available for riscv32.
LLVM implements `version 0.6 of the Qualcomm uC Load Store Multiple extension specification <https://github.com/quic/riscv-unified-db/releases/tag/Xqci-0.13.0>`__ by Qualcomm. These instructions are only available for riscv32.

``experimental-Xqcisim``
LLVM implements `version 0.2 of the Qualcomm uC Simulation Hint extension specification <https://github.com/quic/riscv-unified-db/releases/tag/Xqci-0.11.0>`__ by Qualcomm. These instructions are only available for riscv32.
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17 changes: 9 additions & 8 deletions llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td
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Expand Up @@ -574,9 +574,10 @@ class QCILoadMultiple<bits<2> funct2, DAGOperand InTyRs2, string opcodestr>

// rd corresponds to the source for the store 'rs3' described in the spec.
let hasSideEffects = 0, mayLoad = 0, mayStore = 1 in
class QCIStoreMultiple<bits<2> funct2, DAGOperand InTyRs2, string opcodestr>
class QCIStoreMultiple<bits<2> funct2, DAGOperand InTyRd, DAGOperand InTyRs2,
string opcodestr>
: RVInstRBase<0b111, OPC_CUSTOM_1, (outs),
(ins GPR:$rd, GPR:$rs1, InTyRs2:$rs2, uimm7_lsb00:$imm),
(ins InTyRd:$rd, GPR:$rs1, InTyRs2:$rs2, uimm7_lsb00:$imm),
opcodestr, "$rd, $rs2, ${imm}(${rs1})"> {
bits<7> imm;
let Inst{31-25} = {funct2, imm{6-2}};
Expand Down Expand Up @@ -967,10 +968,10 @@ let Predicates = [HasVendorXqcics, IsRV32] in {
} // Predicates = [HasVendorXqcics, IsRV32]

let Predicates = [HasVendorXqcilsm, IsRV32] in {
def QC_SWM : QCIStoreMultiple<0b00, GPRNoX0, "qc.swm">;
def QC_SWMI : QCIStoreMultiple<0b01, uimm5nonzero, "qc.swmi">;
def QC_SETWM : QCIStoreMultiple<0b10, GPRNoX0, "qc.setwm">;
def QC_SETWMI : QCIStoreMultiple<0b11, uimm5nonzero, "qc.setwmi">;
def QC_SWM : QCIStoreMultiple<0b00, GPRNoX0, GPRNoX0, "qc.swm">;
def QC_SWMI : QCIStoreMultiple<0b01, GPRNoX0, uimm5nonzero, "qc.swmi">;
def QC_SETWM : QCIStoreMultiple<0b10, GPR, GPRNoX0, "qc.setwm">;
def QC_SETWMI : QCIStoreMultiple<0b11, GPR, uimm5nonzero, "qc.setwmi">;

def QC_LWM : QCILoadMultiple<0b00, GPRNoX0, "qc.lwm">;
def QC_LWMI : QCILoadMultiple<0b01, uimm5nonzero, "qc.lwmi">;
Expand Down Expand Up @@ -1211,9 +1212,9 @@ let EmitPriority = 0 in {
let Predicates = [HasVendorXqcilsm, IsRV32] in {
let EmitPriority = 0 in {
def : InstAlias<"qc.swm $rs3, $rs2, (${rs1})",
(QC_SWM GPR:$rs3, GPR:$rs1, GPRNoX0:$rs2, 0)>;
(QC_SWM GPRNoX0:$rs3, GPR:$rs1, GPRNoX0:$rs2, 0)>;
def : InstAlias<"qc.swmi $rs3, $length, (${rs1})",
(QC_SWMI GPR:$rs3, GPR:$rs1, uimm5nonzero:$length, 0)>;
(QC_SWMI GPRNoX0:$rs3, GPR:$rs1, uimm5nonzero:$length, 0)>;
def : InstAlias<"qc.setwm $rs3, $rs2, (${rs1})",
(QC_SETWM GPR:$rs3, GPR:$rs1, GPRNoX0:$rs2, 0)>;
def : InstAlias<"qc.setwmi $rs3, $length, (${rs1})",
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8 changes: 8 additions & 0 deletions llvm/test/MC/RISCV/xqcilsm-invalid.s
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Expand Up @@ -7,6 +7,10 @@
# CHECK: :[[@LINE+1]]:20: error: expected register
qc.swm x5, x20, 12(20)

# CHECK-PLUS: :[[@LINE+2]]:8: error: register must be a GPR excluding zero (x0)
# CHECK-MINUS: :[[@LINE+1]]:8: error: invalid operand for instruction
qc.swm x0, x20, 12(x3)

# CHECK-PLUS: :[[@LINE+2]]:12: error: register must be a GPR excluding zero (x0)
# CHECK-MINUS: :[[@LINE+1]]:12: error: invalid operand for instruction
qc.swm x5, x0, 12(x3)
Expand All @@ -24,6 +28,10 @@ qc.swm x5, x20, 12(x3)
# CHECK: :[[@LINE+1]]:20: error: expected register
qc.swmi x10, 4, 20(4)

# CHECK-PLUS: :[[@LINE+2]]:9: error: register must be a GPR excluding zero (x0)
# CHECK-MINUS: :[[@LINE+1]]:9: error: invalid operand for instruction
qc.swmi x0, 4, 20(x4)

# CHECK: :[[@LINE+1]]:1: error: too few operands for instruction
qc.swmi x10, 4, 20

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