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[AMDGPU] Add GFX12 wave register names with WAVE_ prefix #144352

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Merged
mbrkusanin merged 6 commits into from
Sep 25, 2025
Merged

[AMDGPU] Add GFX12 wave register names with WAVE_ prefix #144352

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43f1a87
[AMDGPU] Add GFX12 wave register names with WAVE_ prefix
aleksandar-amd Jun 16, 2025
3f52226
[AMDGPU] Resolving comments 1
aleksandar-amd Jul 18, 2025
23e5c38
[AMDGPU] Resolving comments 2
aleksandar-amd Sep 25, 2025
5e85570
[AMDGPU] Resolving comments 3
aleksandar-amd Sep 25, 2025
6b1110f
Merge branch 'main' into amdgpu-gfx12-wave-register-names
aleksandar-amd Sep 25, 2025
0f67983
Merge branch 'main' into amdgpu-gfx12-wave-register-names
aleksandar-amd Sep 25, 2025
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166 changes: 79 additions & 87 deletions llvm/lib/Target/AMDGPU/Utils/AMDGPUAsmUtils.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -14,11 +14,9 @@ namespace llvm::AMDGPU {
//===----------------------------------------------------------------------===//
// Custom Operands.
//
// A table of custom operands shall describe "primary" operand names first
// followed by aliases if any. It is not required but recommended to arrange
// operands so that operand encoding match operand position in the table. This
// will make getNameFromOperandTable() a bit more efficient. Unused slots in the
// table shall have an empty name.
// A table of custom operands must be ordered by Encoding in ascending order
// to enable binary search lookup. Within entries that share the same encoding,
// "primary" operand names should be listed first followed by aliases if any.
//
//===----------------------------------------------------------------------===//

Expand All @@ -27,21 +25,18 @@ template <size_t N>
static StringRef getNameFromOperandTable(const CustomOperand (&Table)[N],
unsigned Encoding,
const MCSubtargetInfo &STI) {
auto isValidIndexForEncoding = [&](size_t Idx) {
return Idx < N && Table[Idx].Encoding == Encoding &&
!Table[Idx].Name.empty() &&
(!Table[Idx].Cond || Table[Idx].Cond(STI));
};

// This is an optimization that should work in most cases. As a side effect,
// it may cause selection of an alias instead of a primary operand name in
// case of sparse tables.
if (isValidIndexForEncoding(Encoding))
return Table[Encoding].Name;

for (size_t Idx = 0; Idx != N; ++Idx)
if (isValidIndexForEncoding(Idx))
return Table[Idx].Name;
// Find the first entry with the target encoding
auto First =
std::lower_bound(Table, Table + N, Encoding,
[](const CustomOperand &Entry, unsigned TargetEncoding) {
return Entry.Encoding < TargetEncoding;
});

// Search through entries with the same encoding to find the first valid one
for (auto It = First; It != Table + N && It->Encoding == Encoding; ++It) {
if (It->Encoding == Encoding && (!It->Cond || It->Cond(STI)))
return It->Name;
}

return "";
}
Expand Down Expand Up @@ -92,21 +87,20 @@ namespace SendMsg {
// clang-format off

static constexpr CustomOperand MsgOperands[] = {
{{""}},
{{"MSG_INTERRUPT"}, ID_INTERRUPT},
{{"MSG_GS"}, ID_GS_PreGFX11, isNotGFX11Plus},
{{"MSG_HS_TESSFACTOR"}, ID_HS_TESSFACTOR_GFX11Plus, isGFX11Plus},
{{"MSG_GS_DONE"}, ID_GS_DONE_PreGFX11, isNotGFX11Plus},
{{"MSG_DEALLOC_VGPRS"}, ID_DEALLOC_VGPRS_GFX11Plus, isGFX11Plus},
{{"MSG_SAVEWAVE"}, ID_SAVEWAVE, isGFX8_GFX9_GFX10},
{{"MSG_STALL_WAVE_GEN"}, ID_STALL_WAVE_GEN, isGFX9_GFX10_GFX11},
{{"MSG_HALT_WAVES"}, ID_HALT_WAVES, isGFX9_GFX10_GFX11},
{{"MSG_ORDERED_PS_DONE"}, ID_ORDERED_PS_DONE, isGFX9_GFX10},
{{"MSG_EARLY_PRIM_DEALLOC"}, ID_EARLY_PRIM_DEALLOC, isGFX9_GFX10},
{{"MSG_GS_ALLOC_REQ"}, ID_GS_ALLOC_REQ, isGFX9Plus},
{{"MSG_GET_DOORBELL"}, ID_GET_DOORBELL, isGFX9_GFX10},
{{"MSG_GET_DDID"}, ID_GET_DDID, isGFX10},
{{"MSG_HS_TESSFACTOR"}, ID_HS_TESSFACTOR_GFX11Plus, isGFX11Plus},
{{"MSG_DEALLOC_VGPRS"}, ID_DEALLOC_VGPRS_GFX11Plus, isGFX11Plus},
{{"MSG_SAVEWAVE_HAS_TDM"}, ID_SAVEWAVE_HAS_TDM, isGFX1250},
{{"MSG_GET_DDID"}, ID_GET_DDID, isGFX10},
{{"MSG_SYSMSG"}, ID_SYSMSG},
{{"MSG_RTN_GET_DOORBELL"}, ID_RTN_GET_DOORBELL, isGFX11Plus},
{{"MSG_RTN_GET_DDID"}, ID_RTN_GET_DDID, isGFX11Plus},
Expand All @@ -121,7 +115,6 @@ static constexpr CustomOperand MsgOperands[] = {
};

static constexpr CustomOperand SysMsgOperands[] = {
{{""}},
{{"SYSMSG_OP_ECC_ERR_INTERRUPT"}, OP_SYS_ECC_ERR_INTERRUPT},
{{"SYSMSG_OP_REG_RD"}, OP_SYS_REG_RD},
{{"SYSMSG_OP_HOST_TRAP_ACK"}, OP_SYS_HOST_TRAP_ACK, isNotGFX9Plus},
Expand Down Expand Up @@ -169,68 +162,67 @@ namespace Hwreg {
// NOLINTBEGIN
// clang-format off
static constexpr CustomOperand Operands[] = {
{{""}},
{{"HW_REG_MODE"}, ID_MODE},
{{"HW_REG_STATUS"}, ID_STATUS},
{{"HW_REG_TRAPSTS"}, ID_TRAPSTS, isNotGFX12Plus},
{{"HW_REG_HW_ID"}, ID_HW_ID, isNotGFX10Plus},
{{"HW_REG_GPR_ALLOC"}, ID_GPR_ALLOC},
{{"HW_REG_LDS_ALLOC"}, ID_LDS_ALLOC},
{{"HW_REG_IB_STS"}, ID_IB_STS},
{{""}},
{{""}},
{{"HW_REG_PERF_SNAPSHOT_DATA"}, ID_PERF_SNAPSHOT_DATA_gfx12, isGFX12Plus},
{{"HW_REG_PERF_SNAPSHOT_PC_LO"}, ID_PERF_SNAPSHOT_PC_LO_gfx12, isGFX12Plus},
{{"HW_REG_PERF_SNAPSHOT_PC_HI"}, ID_PERF_SNAPSHOT_PC_HI_gfx12, isGFX12Plus},
{{""}},
{{""}},
{{"HW_REG_SH_MEM_BASES"}, ID_MEM_BASES, isGFX9_GFX10_GFX11},
{{"HW_REG_TBA_LO"}, ID_TBA_LO, isGFX9_GFX10},
{{"HW_REG_TBA_HI"}, ID_TBA_HI, isGFX9_GFX10},
{{"HW_REG_TMA_LO"}, ID_TMA_LO, isGFX9_GFX10},
{{"HW_REG_TMA_HI"}, ID_TMA_HI, isGFX9_GFX10},
{{"HW_REG_FLAT_SCR_LO"}, ID_FLAT_SCR_LO, isGFX10_GFX11},
{{"HW_REG_FLAT_SCR_HI"}, ID_FLAT_SCR_HI, isGFX10_GFX11},
{{"HW_REG_XNACK_MASK"}, ID_XNACK_MASK, isGFX10Before1030},
{{"HW_REG_HW_ID1"}, ID_HW_ID1, isGFX10Plus},
{{"HW_REG_HW_ID2"}, ID_HW_ID2, isGFX10Plus},
{{"HW_REG_POPS_PACKER"}, ID_POPS_PACKER, isGFX10},
{{""}},
{{"HW_REG_PERF_SNAPSHOT_DATA"}, ID_PERF_SNAPSHOT_DATA_gfx11, isGFX11},
{{"HW_REG_IB_STS2"}, ID_IB_STS2, isGFX1250},
{{"HW_REG_SHADER_CYCLES"}, ID_SHADER_CYCLES, isGFX10_3_GFX11},
{{"HW_REG_SHADER_CYCLES_HI"}, ID_SHADER_CYCLES_HI, isGFX12Plus},
{{"HW_REG_DVGPR_ALLOC_LO"}, ID_DVGPR_ALLOC_LO, isGFX12Plus},
{{"HW_REG_DVGPR_ALLOC_HI"}, ID_DVGPR_ALLOC_HI, isGFX12Plus},

// Register numbers reused in GFX11
{{"HW_REG_PERF_SNAPSHOT_PC_LO"}, ID_PERF_SNAPSHOT_PC_LO_gfx11, isGFX11},
{{"HW_REG_PERF_SNAPSHOT_PC_HI"}, ID_PERF_SNAPSHOT_PC_HI_gfx11, isGFX11},

// Register numbers reused in GFX12+
{{"HW_REG_STATE_PRIV"}, ID_STATE_PRIV, isGFX12Plus},
{{"HW_REG_PERF_SNAPSHOT_DATA1"}, ID_PERF_SNAPSHOT_DATA1, isGFX12Plus},
{{"HW_REG_PERF_SNAPSHOT_DATA2"}, ID_PERF_SNAPSHOT_DATA2, isGFX12Plus},
{{"HW_REG_EXCP_FLAG_PRIV"}, ID_EXCP_FLAG_PRIV, isGFX12Plus},
{{"HW_REG_EXCP_FLAG_USER"}, ID_EXCP_FLAG_USER, isGFX12Plus},
{{"HW_REG_TRAP_CTRL"}, ID_TRAP_CTRL, isGFX12Plus},
{{"HW_REG_SCRATCH_BASE_LO"}, ID_FLAT_SCR_LO, isGFX12Plus},
{{"HW_REG_SCRATCH_BASE_HI"}, ID_FLAT_SCR_HI, isGFX12Plus},
{{"HW_REG_SHADER_CYCLES_LO"}, ID_SHADER_CYCLES, isGFX12Plus},

// GFX942 specific registers
{{"HW_REG_XCC_ID"}, ID_XCC_ID, isGFX940},
{{"HW_REG_SQ_PERF_SNAPSHOT_DATA"}, ID_SQ_PERF_SNAPSHOT_DATA, isGFX940},
{{"HW_REG_SQ_PERF_SNAPSHOT_DATA1"}, ID_SQ_PERF_SNAPSHOT_DATA1, isGFX940},
{{"HW_REG_SQ_PERF_SNAPSHOT_PC_LO"}, ID_SQ_PERF_SNAPSHOT_PC_LO, isGFX940},
{{"HW_REG_SQ_PERF_SNAPSHOT_PC_HI"}, ID_SQ_PERF_SNAPSHOT_PC_HI, isGFX940},

// GFX1250
{{"HW_REG_XNACK_STATE_PRIV"}, ID_XNACK_STATE_PRIV, isGFX1250},
{{"HW_REG_XNACK_MASK"}, ID_XNACK_MASK_gfx1250, isGFX1250},

// Aliases
{{"HW_REG_HW_ID"}, ID_HW_ID1, isGFX10},
{{"HW_REG_WAVE_MODE"}, ID_MODE, isGFX12Plus},
{{"HW_REG_MODE"}, ID_MODE},
{{"HW_REG_WAVE_STATUS"}, ID_STATUS, isGFX12Plus},
{{"HW_REG_STATUS"}, ID_STATUS},
{{"HW_REG_TRAPSTS"}, ID_TRAPSTS, isNotGFX12Plus},
{{"HW_REG_HW_ID"}, ID_HW_ID, isNotGFX10Plus},
{{"HW_REG_WAVE_STATE_PRIV"}, ID_STATE_PRIV, isGFX12Plus},
{{"HW_REG_STATE_PRIV"}, ID_STATE_PRIV, isGFX12Plus},
{{"HW_REG_WAVE_GPR_ALLOC"}, ID_GPR_ALLOC, isGFX12Plus},
{{"HW_REG_GPR_ALLOC"}, ID_GPR_ALLOC},
{{"HW_REG_WAVE_LDS_ALLOC"}, ID_LDS_ALLOC, isGFX12Plus},
{{"HW_REG_LDS_ALLOC"}, ID_LDS_ALLOC},
{{"HW_REG_IB_STS"}, ID_IB_STS},
{{"HW_REG_PERF_SNAPSHOT_DATA"}, ID_PERF_SNAPSHOT_DATA_gfx12, isGFX12Plus},
{{"HW_REG_PERF_SNAPSHOT_PC_LO"}, ID_PERF_SNAPSHOT_PC_LO_gfx12, isGFX12Plus},
{{"HW_REG_PERF_SNAPSHOT_PC_HI"}, ID_PERF_SNAPSHOT_PC_HI_gfx12, isGFX12Plus},
{{"HW_REG_SH_MEM_BASES"}, ID_MEM_BASES, isGFX9_GFX10_GFX11},
{{"HW_REG_PERF_SNAPSHOT_DATA1"}, ID_PERF_SNAPSHOT_DATA1, isGFX12Plus},
{{"HW_REG_TBA_LO"}, ID_TBA_LO, isGFX9_GFX10},
{{"HW_REG_PERF_SNAPSHOT_DATA2"}, ID_PERF_SNAPSHOT_DATA2, isGFX12Plus},
{{"HW_REG_TBA_HI"}, ID_TBA_HI, isGFX9_GFX10},
{{"HW_REG_WAVE_EXCP_FLAG_PRIV"}, ID_EXCP_FLAG_PRIV, isGFX12Plus},
{{"HW_REG_EXCP_FLAG_PRIV"}, ID_EXCP_FLAG_PRIV, isGFX12Plus},
{{"HW_REG_TMA_LO"}, ID_TMA_LO, isGFX9_GFX10},
{{"HW_REG_PERF_SNAPSHOT_PC_LO"}, ID_PERF_SNAPSHOT_PC_LO_gfx11, isGFX11},
{{"HW_REG_WAVE_EXCP_FLAG_USER"}, ID_EXCP_FLAG_USER, isGFX12Plus},
{{"HW_REG_EXCP_FLAG_USER"}, ID_EXCP_FLAG_USER, isGFX12Plus},
{{"HW_REG_TMA_HI"}, ID_TMA_HI, isGFX9_GFX10},
{{"HW_REG_PERF_SNAPSHOT_PC_HI"}, ID_PERF_SNAPSHOT_PC_HI_gfx11, isGFX11},
{{"HW_REG_WAVE_TRAP_CTRL"}, ID_TRAP_CTRL, isGFX12Plus},
{{"HW_REG_TRAP_CTRL"}, ID_TRAP_CTRL, isGFX12Plus},
{{"HW_REG_FLAT_SCR_LO"}, ID_FLAT_SCR_LO, isGFX10_GFX11},
{{"HW_REG_WAVE_SCRATCH_BASE_LO"}, ID_FLAT_SCR_LO, isGFX12Plus},
{{"HW_REG_SCRATCH_BASE_LO"}, ID_FLAT_SCR_LO, isGFX12Plus},
{{"HW_REG_XCC_ID"}, ID_XCC_ID, isGFX940},
{{"HW_REG_FLAT_SCR_HI"}, ID_FLAT_SCR_HI, isGFX10_GFX11},
{{"HW_REG_WAVE_SCRATCH_BASE_HI"}, ID_FLAT_SCR_HI, isGFX12Plus},
{{"HW_REG_SCRATCH_BASE_HI"}, ID_FLAT_SCR_HI, isGFX12Plus},
{{"HW_REG_SQ_PERF_SNAPSHOT_DATA"}, ID_SQ_PERF_SNAPSHOT_DATA, isGFX940},
{{"HW_REG_XNACK_MASK"}, ID_XNACK_MASK, isGFX10Before1030},
{{"HW_REG_SQ_PERF_SNAPSHOT_DATA1"}, ID_SQ_PERF_SNAPSHOT_DATA1, isGFX940},
{{"HW_REG_WAVE_HW_ID1"}, ID_HW_ID1, isGFX12Plus},
{{"HW_REG_HW_ID1"}, ID_HW_ID1, isGFX10Plus},
{{"HW_REG_HW_ID"}, ID_HW_ID1, isGFX10},
{{"HW_REG_SQ_PERF_SNAPSHOT_PC_LO"}, ID_SQ_PERF_SNAPSHOT_PC_LO, isGFX940},
{{"HW_REG_WAVE_HW_ID2"}, ID_HW_ID2, isGFX12Plus},
{{"HW_REG_HW_ID2"}, ID_HW_ID2, isGFX10Plus},
{{"HW_REG_SQ_PERF_SNAPSHOT_PC_HI"}, ID_SQ_PERF_SNAPSHOT_PC_HI, isGFX940},
{{"HW_REG_POPS_PACKER"}, ID_POPS_PACKER, isGFX10},
{{"HW_REG_PERF_SNAPSHOT_DATA"}, ID_PERF_SNAPSHOT_DATA_gfx11, isGFX11},
{{"HW_REG_IB_STS2"}, ID_IB_STS2, isGFX1250},
{{"HW_REG_SHADER_CYCLES"}, ID_SHADER_CYCLES, isGFX10_3_GFX11},
{{"HW_REG_SHADER_CYCLES_LO"}, ID_SHADER_CYCLES, isGFX12Plus},
{{"HW_REG_SHADER_CYCLES_HI"}, ID_SHADER_CYCLES_HI, isGFX12Plus},
{{"HW_REG_WAVE_DVGPR_ALLOC_LO"}, ID_DVGPR_ALLOC_LO, isGFX12Plus},
{{"HW_REG_DVGPR_ALLOC_LO"}, ID_DVGPR_ALLOC_LO, isGFX12Plus},
{{"HW_REG_WAVE_DVGPR_ALLOC_HI"}, ID_DVGPR_ALLOC_HI, isGFX12Plus},
{{"HW_REG_DVGPR_ALLOC_HI"}, ID_DVGPR_ALLOC_HI, isGFX12Plus},
{{"HW_REG_XNACK_STATE_PRIV"}, ID_XNACK_STATE_PRIV, isGFX1250},
{{"HW_REG_XNACK_MASK"}, ID_XNACK_MASK_gfx1250, isGFX1250},

};
// clang-format on
// NOLINTEND
Expand Down
28 changes: 14 additions & 14 deletions llvm/test/CodeGen/AMDGPU/dynamic-vgpr-reserve-stack-for-cwsr.ll
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Original file line number Diff line number Diff line change
Expand Up @@ -7,7 +7,7 @@
define amdgpu_cs void @amdgpu_cs() #0 {
; CHECK-LABEL: amdgpu_cs:
; CHECK: ; %bb.0:
; CHECK-NEXT: s_getreg_b32 s33, hwreg(HW_REG_HW_ID2, 8, 2)
; CHECK-NEXT: s_getreg_b32 s33, hwreg(HW_REG_WAVE_HW_ID2, 8, 2)
; CHECK-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; CHECK-NEXT: s_cmp_lg_u32 0, s33
; CHECK-NEXT: s_cmovk_i32 s33, 0x1c0
Expand All @@ -19,7 +19,7 @@ define amdgpu_cs void @amdgpu_cs() #0 {
define amdgpu_kernel void @kernel() #0 {
; CHECK-LABEL: kernel:
; CHECK: ; %bb.0:
; CHECK-NEXT: s_getreg_b32 s33, hwreg(HW_REG_HW_ID2, 8, 2)
; CHECK-NEXT: s_getreg_b32 s33, hwreg(HW_REG_WAVE_HW_ID2, 8, 2)
; CHECK-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; CHECK-NEXT: s_cmp_lg_u32 0, s33
; CHECK-NEXT: s_cmovk_i32 s33, 0x1c0
Expand All @@ -31,7 +31,7 @@ define amdgpu_kernel void @kernel() #0 {
define amdgpu_cs void @with_local() #0 {
; CHECK-TRUE16-LABEL: with_local:
; CHECK-TRUE16: ; %bb.0:
; CHECK-TRUE16-NEXT: s_getreg_b32 s33, hwreg(HW_REG_HW_ID2, 8, 2)
; CHECK-TRUE16-NEXT: s_getreg_b32 s33, hwreg(HW_REG_WAVE_HW_ID2, 8, 2)
; CHECK-TRUE16-NEXT: v_mov_b16_e32 v0.l, 13
; CHECK-TRUE16-NEXT: s_cmp_lg_u32 0, s33
; CHECK-TRUE16-NEXT: s_cmovk_i32 s33, 0x1c0
Expand All @@ -42,7 +42,7 @@ define amdgpu_cs void @with_local() #0 {
;
; CHECK-FAKE16-LABEL: with_local:
; CHECK-FAKE16: ; %bb.0:
; CHECK-FAKE16-NEXT: s_getreg_b32 s33, hwreg(HW_REG_HW_ID2, 8, 2)
; CHECK-FAKE16-NEXT: s_getreg_b32 s33, hwreg(HW_REG_WAVE_HW_ID2, 8, 2)
; CHECK-FAKE16-NEXT: v_mov_b32_e32 v0, 13
; CHECK-FAKE16-NEXT: s_cmp_lg_u32 0, s33
; CHECK-FAKE16-NEXT: s_cmovk_i32 s33, 0x1c0
Expand All @@ -60,7 +60,7 @@ define amdgpu_cs void @with_local() #0 {
define amdgpu_cs void @with_calls_inline_const() #0 {
; CHECK-TRUE16-LABEL: with_calls_inline_const:
; CHECK-TRUE16: ; %bb.0:
; CHECK-TRUE16-NEXT: s_getreg_b32 s33, hwreg(HW_REG_HW_ID2, 8, 2)
; CHECK-TRUE16-NEXT: s_getreg_b32 s33, hwreg(HW_REG_WAVE_HW_ID2, 8, 2)
; CHECK-TRUE16-NEXT: v_mov_b16_e32 v0.l, 15
; CHECK-TRUE16-NEXT: s_cmp_lg_u32 0, s33
; CHECK-TRUE16-NEXT: s_mov_b32 s1, callee@abs32@hi
Expand All @@ -76,7 +76,7 @@ define amdgpu_cs void @with_calls_inline_const() #0 {
;
; CHECK-FAKE16-LABEL: with_calls_inline_const:
; CHECK-FAKE16: ; %bb.0:
; CHECK-FAKE16-NEXT: s_getreg_b32 s33, hwreg(HW_REG_HW_ID2, 8, 2)
; CHECK-FAKE16-NEXT: s_getreg_b32 s33, hwreg(HW_REG_WAVE_HW_ID2, 8, 2)
; CHECK-FAKE16-NEXT: v_mov_b32_e32 v0, 15
; CHECK-FAKE16-NEXT: s_cmp_lg_u32 0, s33
; CHECK-FAKE16-NEXT: s_mov_b32 s1, callee@abs32@hi
Expand All @@ -100,7 +100,7 @@ define amdgpu_cs void @with_calls_inline_const() #0 {
define amdgpu_cs void @with_calls_no_inline_const() #0 {
; CHECK-TRUE16-LABEL: with_calls_no_inline_const:
; CHECK-TRUE16: ; %bb.0:
; CHECK-TRUE16-NEXT: s_getreg_b32 s33, hwreg(HW_REG_HW_ID2, 8, 2)
; CHECK-TRUE16-NEXT: s_getreg_b32 s33, hwreg(HW_REG_WAVE_HW_ID2, 8, 2)
; CHECK-TRUE16-NEXT: v_mov_b16_e32 v0.l, 15
; CHECK-TRUE16-NEXT: s_cmp_lg_u32 0, s33
; CHECK-TRUE16-NEXT: s_mov_b32 s1, callee@abs32@hi
Expand All @@ -117,7 +117,7 @@ define amdgpu_cs void @with_calls_no_inline_const() #0 {
;
; CHECK-FAKE16-LABEL: with_calls_no_inline_const:
; CHECK-FAKE16: ; %bb.0:
; CHECK-FAKE16-NEXT: s_getreg_b32 s33, hwreg(HW_REG_HW_ID2, 8, 2)
; CHECK-FAKE16-NEXT: s_getreg_b32 s33, hwreg(HW_REG_WAVE_HW_ID2, 8, 2)
; CHECK-FAKE16-NEXT: v_mov_b32_e32 v0, 15
; CHECK-FAKE16-NEXT: s_cmp_lg_u32 0, s33
; CHECK-FAKE16-NEXT: s_mov_b32 s1, callee@abs32@hi
Expand All @@ -140,7 +140,7 @@ define amdgpu_cs void @with_calls_no_inline_const() #0 {
define amdgpu_cs void @with_spills() #0 {
; CHECK-LABEL: with_spills:
; CHECK: ; %bb.0:
; CHECK-NEXT: s_getreg_b32 s33, hwreg(HW_REG_HW_ID2, 8, 2)
; CHECK-NEXT: s_getreg_b32 s33, hwreg(HW_REG_WAVE_HW_ID2, 8, 2)
; CHECK-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; CHECK-NEXT: s_cmp_lg_u32 0, s33
; CHECK-NEXT: s_cmovk_i32 s33, 0x1c0
Expand All @@ -153,7 +153,7 @@ define amdgpu_cs void @with_spills() #0 {
define amdgpu_cs void @realign_stack(<32 x i32> %x) #0 {
; CHECK-LABEL: realign_stack:
; CHECK: ; %bb.0:
; CHECK-NEXT: s_getreg_b32 s33, hwreg(HW_REG_HW_ID2, 8, 2)
; CHECK-NEXT: s_getreg_b32 s33, hwreg(HW_REG_WAVE_HW_ID2, 8, 2)
; CHECK-NEXT: v_mov_b32_e32 v32, 0
; CHECK-NEXT: s_cmp_lg_u32 0, s33
; CHECK-NEXT: s_mov_b32 s1, callee@abs32@hi
Expand Down Expand Up @@ -187,7 +187,7 @@ define amdgpu_cs void @realign_stack(<32 x i32> %x) #0 {
define amdgpu_cs void @frame_pointer_none() #1 {
; CHECK-TRUE16-LABEL: frame_pointer_none:
; CHECK-TRUE16: ; %bb.0:
; CHECK-TRUE16-NEXT: s_getreg_b32 s33, hwreg(HW_REG_HW_ID2, 8, 2)
; CHECK-TRUE16-NEXT: s_getreg_b32 s33, hwreg(HW_REG_WAVE_HW_ID2, 8, 2)
; CHECK-TRUE16-NEXT: v_mov_b16_e32 v0.l, 13
; CHECK-TRUE16-NEXT: s_cmp_lg_u32 0, s33
; CHECK-TRUE16-NEXT: s_cmovk_i32 s33, 0x1c0
Expand All @@ -198,7 +198,7 @@ define amdgpu_cs void @frame_pointer_none() #1 {
;
; CHECK-FAKE16-LABEL: frame_pointer_none:
; CHECK-FAKE16: ; %bb.0:
; CHECK-FAKE16-NEXT: s_getreg_b32 s33, hwreg(HW_REG_HW_ID2, 8, 2)
; CHECK-FAKE16-NEXT: s_getreg_b32 s33, hwreg(HW_REG_WAVE_HW_ID2, 8, 2)
; CHECK-FAKE16-NEXT: v_mov_b32_e32 v0, 13
; CHECK-FAKE16-NEXT: s_cmp_lg_u32 0, s33
; CHECK-FAKE16-NEXT: s_cmovk_i32 s33, 0x1c0
Expand All @@ -214,7 +214,7 @@ define amdgpu_cs void @frame_pointer_none() #1 {
define amdgpu_cs void @frame_pointer_all() #2 {
; CHECK-TRUE16-LABEL: frame_pointer_all:
; CHECK-TRUE16: ; %bb.0:
; CHECK-TRUE16-NEXT: s_getreg_b32 s33, hwreg(HW_REG_HW_ID2, 8, 2)
; CHECK-TRUE16-NEXT: s_getreg_b32 s33, hwreg(HW_REG_WAVE_HW_ID2, 8, 2)
; CHECK-TRUE16-NEXT: v_mov_b16_e32 v0.l, 13
; CHECK-TRUE16-NEXT: s_cmp_lg_u32 0, s33
; CHECK-TRUE16-NEXT: s_cmovk_i32 s33, 0x1c0
Expand All @@ -225,7 +225,7 @@ define amdgpu_cs void @frame_pointer_all() #2 {
;
; CHECK-FAKE16-LABEL: frame_pointer_all:
; CHECK-FAKE16: ; %bb.0:
; CHECK-FAKE16-NEXT: s_getreg_b32 s33, hwreg(HW_REG_HW_ID2, 8, 2)
; CHECK-FAKE16-NEXT: s_getreg_b32 s33, hwreg(HW_REG_WAVE_HW_ID2, 8, 2)
; CHECK-FAKE16-NEXT: v_mov_b32_e32 v0, 13
; CHECK-FAKE16-NEXT: s_cmp_lg_u32 0, s33
; CHECK-FAKE16-NEXT: s_cmovk_i32 s33, 0x1c0
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